Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.
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Updated
Jul 15, 2023 - SystemVerilog
Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.
Hardware Abstraction Layer for Atmosic SoCs in the Zephyr Environment
HTTP request/response parser in C tuned for low-profile MCUs like Arduino
openbmc Baseboard Management Controller
Convolutional Neural Networks for Verilog High-Level Synthesis
COM 5242 Introduction to SoC and its Applications 2022 Course Materials
This is an ongoing rewrite of https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/SocExplorer
System-Verilog implementation of the ACDMA crossbar
SideLine is a software-based power side-channel analysis vector. It uses delay-lines (located in SoC memory controllers) as power meters.
The goal of ECE 385 course is to teach students to design, build, and test/debug a digital system, which can be a 16-bit microprocessor, a dedicated logic core, or a system-on-a-chip (SoC) platform
Examples of using Litex on an Alchitry Cu board
All projects that utilize VHDL.
RISC-V SoC
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