Pequeno aka pqr5 is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I
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Updated
Apr 6, 2024 - SystemVerilog
Pequeno aka pqr5 is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I
Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
16 bit serial multiplier in SystemVerilog
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
Synthesizable SystemVerilog IP-Core of the I2S Receiver
Pulse Width Modulator programmed through an Advanced Peripheral Bus interface
Quartus II project for a basic interface for writing in a LCD screen using a PS2 keyboard using Altera DE2-70 board
RISC-V five stage pipline CPU
UVM Test bench for a 8-bit ALU
A systemverilog implementation of the data structures: priority queue, queue and stack
Multiple DUT with parallel stimulus
Verilog Codes for various Design
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
This testbench is based on SV and UVM Class based to verify Verilog HDL Design
Proyecto Final para el curso de Taller de Diseño Digital. La idea es hacer un procesador uniciclo para procesar un texto utilizando los lenguajes de programación ARM, Python y SystemVerilog.
An FPGA-based Chess Engine and TPU
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
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