testbench
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VUnit is a unit testing framework for VHDL/SystemVerilog
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Jun 12, 2024 - VHDL
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
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Jun 12, 2024 - VHDL
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
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Jun 10, 2024 - VHDL
Examples and design pattern for VHDL verification
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Apr 10, 2016 - VHDL
Custom 64-bit pipelined RISC processor
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Feb 11, 2023 - VHDL
Bus functional model of an Enhanced Serial Peripheral Interface (eSPI) master
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Jun 7, 2022 - VHDL
Deluxe RISC processor
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Sep 17, 2020 - VHDL
basic simulations of digital electronics using vhdl
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Jan 7, 2017 - VHDL
Contains VHDL netlists of basic digital circuits.
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Mar 9, 2019 - VHDL
Practical application of the hardware description language on the example of the standard player control device. Modeling the behavioral model, verification and obtaining the final result, depicted on the waveform. The control device and verification described with VHDL.
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Jan 16, 2022 - VHDL
CPU Design project for the course "Application and Design of Digital Logic" at Glasgow College, UESTC .
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Mar 26, 2024 - VHDL
Hardware testbench project for the Mini-EUSO L2 trigger (HLS implementation)
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Jul 10, 2019 - VHDL
Diseño de un circuito secuencial con entrada de datos x de 1 bit, una entrada de reset y una entrada de reloj. El sistema es un detector de secuencia que genera una salida z de 1 bit con ‘1’ cuando los últimos cuatro bits recibidos en x son 0101. El circuito se diseña de diversas maneras, cada una de ellas con una descripción en VHDL
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Sep 29, 2022 - VHDL
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