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uvm

Here are 12 public repositories matching this topic...

Juniper / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

asic fpga eda systemverilog uvm registers systemrdl jspec register-descriptions systemrdl-compiler

Updated Jul 28, 2023
Verilog

gupta409 / Processor-UVM-Verification

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

processor verilog systemverilog uvm verilog-hdl systemverilog-simulation

Updated Jan 17, 2018
Verilog

erihsu / INT_FP_MAC

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

verilog systemverilog uvm accumulator

Updated Sep 27, 2020
Verilog

amamory-verification / uvm-basics

my UVM training projects

systemverilog uvm verification-methodologies constrained-random-verification

Updated Mar 14, 2019
Verilog

sdnellen / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design

Updated Jan 31, 2024
Verilog

rooinasuit / AXI_to_SPI

Designing means to communicate as an SPI master, being a part of AXI interface

fpga verilog spi systemverilog uvm functional-verification axi-lite

Updated Sep 14, 2023
Verilog

Pirate-Emperor / CipherX

CipherX is a verification project for Advanced Encryption Standard (AES-128) using Universal Verification Methodology (UVM). It leverages Verilog, SystemVerilog, and Python to ensure robust encryption algorithm validation, integrating comprehensive UVM components and tests.

python security cryptography encryption verification aes-128 verilog uvm cryptography-algorithms digitaldesign dataencryption hardwareverification dataencryptionstandards testingframeworks

Updated Aug 24, 2024
Verilog

Crimsonninja / elen613

Code for ELEN613: SOC Verification

uvm

Updated Nov 2, 2022
Verilog

midimaster21b / SHA-Module

A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.

vhdl verilog systemverilog uvm fusesoc

Updated Oct 23, 2022
Verilog

yuravg / uvm_book_examples

UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition by Kathleen Meade and Sharon Rosenberg

verification systemverilog uvm

Updated Sep 3, 2024
Verilog

ahmd-kamel / UART-Verilog-Design

Design and Verification of UART IP that allows serial communication between two systems.

rtl systemverilog uvm verilog-hdl uart-protocol serial-communication

Updated Sep 1, 2024
Verilog

ganesh-rgb / VLSI-Design-Projects-

Electronics Circuit Design and Verification

verilog systemverilog uvm uvm-ral-model digitalelectronics analog-circuit-design testbench-development

Updated Aug 14, 2024
Verilog

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