A project by Verilog HDL to play the whac-a-mole game on BASYS 2 FPGA board.
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Updated
Sep 25, 2019 - Verilog
A project by Verilog HDL to play the whac-a-mole game on BASYS 2 FPGA board.
A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.
A pipelined implementation of MIPS32 processor using Verilog HDL
Open Source Verilog Modules
This repository focuses on how to design a PWM Generator with variable Duty cycle
Some exercises on verilog.
All basic to advanced hardware models which are used in VLSI Frontend Design using Verilog HDL
An 4-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.
32 bits ALU include 16 commands to run/Verilog Code (.v) + Digital Circuit (.circ)
Verilog structural model HDL program
Contains CSE460 Group Project Verilog code.
In CMPSC 331 2019, I implemented a design of 32-bit-pipelined cpu design.
Verilog programs for VIT Vellore Digital System Design Lab course (2023)
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