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vhdl

Here are 106 public repositories matching this topic...

npatsiatzis / fifo_asynchronous

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 8, 2023
Python

npatsiatzis / cdc_handshake

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 9, 2023
Python

npatsiatzis / recirculation_mux

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 9, 2023
Python

npatsiatzis / fizzbuzz

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 7, 2023
Python

JochiSt / pyVHDLinstTemplate

create a VHDL instantiation template from Verilog source

vhdl python-script verilog verilog-hdl language-converter

Updated Feb 26, 2024
Python

GargiMan / inp

Projects made for INP (Design of Computer Systems)

assembly vhdl brainfuck fit vut inp 2022

Updated Dec 18, 2022
Python

diwenshi61 / Barrett_Reduction

A python script that generates VHDL files describing steps for a modular reduction in hardware

python vhdl modular-arithmetic

Updated Feb 15, 2020
Python

rowantwilley16 / image-calibration-algorithms

python vhdl image-processing image-calibration

Updated May 15, 2024
Python

thisisfrey / VHDLinter

Small linter for VHDL

linter vhdl vhdl-linter

Updated Apr 26, 2020
Python

connorcl / testbench-gen

A simple VHDL test bench generator (for combinational logic) written in Python

python vhdl python3 vhdl-testbench

Updated May 13, 2020
Python

npatsiatzis / fir

vhdl systemverilog verilator cocotb sby pyuvm

Updated Oct 8, 2023
Python

PyFPGA / hdl2vlog

VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.

vhdl verilog systemverilog yosys ghdl-yosys-plugin synlig

Updated Feb 4, 2024
Python

Verkhovskaya / pywire

An easy-to-use Python library for generating VHDL, designed for use with FPGAs.

python fpga hardware vhdl ucf

Updated Sep 17, 2018
Python

jacobgualtieri / VHDL_Port_Map_Generator

This is a python script that automatically generates testbench templates for Verilog and VHDL source files. It parses the provided HDL source file for a module's name, parameters, and ports and then writes a testbench template for that module. This can be used to automate and streamline the process of setting up simulations for your HDL modules.…

automation simulation scripting vhdl python3 verilog testbench

Updated Jul 3, 2021
Python

dave2pi / SublimeLinter-contrib-vcom

SublimeLinter plugin for linting VHDL with Modelsim vcom

vhdl sublimelinter modelsim questasim sublimelinter-plugin

Updated Dec 21, 2017
Python

jimmykizito / aHdlTemplate

A template for test-driven HDL development.

fpga vhdl verilog hdl

Updated Jun 15, 2020
Python

DRubioG / HDLHelper

HDL Tools for programming VHDL and Verilog

python vhdl verilog testbench

Updated Jun 2, 2024
Python

hclhls / learn_hwt

Examples with HWToolkit (A Python-based hardware construction framework)

fpga vhdl rtl verilog hcl hardware-designs

Updated Mar 26, 2024
Python

esynr3z / pip-hdl

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

python vhdl verification vip pip verilog systemverilog ip-core rtl-design

Updated Jan 26, 2024
Python

intrepidcs / vhdllint

VHDL linter tool based on cpplint

lint fpga linter vhdl

Updated Apr 28, 2023
Python

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