A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
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Sep 4, 2024 - SystemVerilog
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vlsi-design
Here are 6 public repositories matching this topic...
Spiking Neural Network Accelerator
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May 18, 2022 - SystemVerilog
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
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May 9, 2022 - SystemVerilog
Verilog-Training-5-stage-Pipeline-CPU
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Oct 13, 2024 - SystemVerilog
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
asic
verification
verilog
systemverilog
soc
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vlsi-design
systemverilog-examples
systemverilog-problems
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Mar 31, 2023 - SystemVerilog
SystemVerilog verification of I2C interface
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Dec 12, 2023 - SystemVerilog
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