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Integrating your image processing HDL code with the platform

philippemilletresearch edited this page Jan 28, 2019 · 9 revisions

Guideline Information

Item Value
Guideline Number 15
Guideline Responsible (Name, Affiliation) Fatima Kishwar, Sundance
Guideline Reviewer (Name, Affiliation) Magnus Jahre, NTNU
Guideline Audience (Category) Toolchain designers, Application developers, System architects
Guideline Expertise (Category) HW designers
Guideline Keywords (Category) FPGA, System optimisation

Guideline advice

If you have a HDL code that can do part of the processing, you can integrate it with your SDSoC design via IP creation in Vivado.

Insights that led to the guideline

Certain applications need to use legacy HDL modules to interface with certain peripherals (where Xilinx IP’s are not present) or interface third party IP’s or have a legacy module written in HDL to be used in the project design.Feature-based Simultaneous Localization and Mapping (SLAM) algorithm have as the first processing step the feature detection and description task. The availability of HDL based implementations for some functions like Harris or FAST corner detection can be utilized within an SDSoC Project.

Recommended implementation method of the guideline along with a solid motivation for the recommendation

The implementation of such a design depends on the requirement of the application. Certain applications needs as an input the processed data and the image data. In that case creating the Vivado platform require both AXI Video DMA (VDMA) for image acquisition and DMA for processed data (in the case of ORB descriptor, it would be the corner position and the binary descriptor of the corner).

Instantiation of the recommended implementation method in the reference platform

Two kind of Cameras are used in TULIPP's projects, HDMI-based and Cameralink-based Camera. The combination of EMC2 and Avnet HDMI Input/Output FMC board was used in the Sobel and motion detection demo. Integrating HDL with this platform require finding-out the stream of pixels and the synchronization signals. Custom HDL code for the Avnet hardware module is provided to use with the board and needed to be integrated with the AXI based design of the project; this was done using the IP integration tool present in the Vivado toolset.

Evaluation of the guideline in reference applications

This was tested both by Sundance and Hipperos during their demos implementation.

References

Review

Related guidelines

none

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