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Review of Guideline #6

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aripod edited this page Aug 27, 2018 · 8 revisions

Review of Guideline #6

Formatting

Item Outcome
Guideline complies with the Guideline-Template Yes
Name of guideline responsible with affiliation is clearly stated Yes

Is the audience of the guideline correctly specified?

Yes it is. The guideline is meant for software and hardware developers. It is explicitly mentioned in the Guideline advice what has to be done for CPUs and FPGAs.

Is the expertise required to write the guideline correctly specified?

Yes. Software and Hardware expertise is needed.

Are the keywords well selected?

Yes, but this could be improved. When suggesting to store most frequently accessed data in internal FPGA memory, it would be nice to specify what "internal FPGA memory" means. FIFO? BRAM? Maybe some sentences on how to achieve this or some reference to point to the right guide.

Are parts of the guideline too generic or too specific?

The guideline is very specific to the potential issue it refers to and provides a solution to avoid it.

Does the guideline explicitly refer to the handbook? To which part of the deliverable is it relevant (e.g., chapter of D1.2/D1.3)?

No

Does the guideline specify the work done in the project that can benefit from the guideline?

Yes, it that it will be applied to the use cases.

Other comments

  1. Guideline advice: Split the second paragraph in two. Make the sentence "For FPGA based systems..." a new one. Otherwise, it is a very long sentence: For CPU implementations, this means to maximize the utilization of the memory cache. For FPGA based systems, it means to find a structure where most data accesses use the FPGA internal memory.

  2. Insights that led to the guideline: Small detail, first you write FPGA/cache memory and the order is inverted.

  3. Recommended implementation method of the guideline along with a solid motivation for the recommendation: If an FPGA is your target, try to understand how much of the internal memory can be allocated to this part of the algorithm.

  4. Instantiation of the recommended implementation method in the reference platform:

  5. Evaluation of the guideline in reference applications:

  6. References: None. Maybe something to help the designer with FPGA internal memory.

Track changes:

  1. 30/07/2018: Made some formatting changes in the guidelines to cope with template.
  2. 23/08/2018: Guideline reviewed.

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