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Review of Guideline #5
| Item | Outcome |
|---|---|
| Guideline complies with the Guideline-Template | Yes |
| Name of guideline responsible with affiliation is clearly stated | Yes |
Yes. The guideline is relevant for people that make high-level architecture decisions (i.e., system architects) and people tasked with realising specified hardware functions (i.e., hardware designers).
Yes. Hardware design expertise is necessary.
No. The guideline is mainly about IP core selection. If a using particular IP core is a requirement, it will also limt the choice of computing platform. Thus, the keywords should be "IP core selection" and "Platform selection". Feel free to add other keywords.
The current keyword "Critical component selection" is OK, but imprecise. The guideline does not provide insights regarding CPU selection.
The guideline gives a nice overview of how to choose IP cores. ASIC design is hardly covered and seems of little relevance to both the key message of the guideline and TULIPP. I suggest that the guideline is renamed to something along the lines of "IP core selection for FPGA-based image processing platforms" and that the discussion of ASICs is removed.
FC: hmmmm.. - the thinking was me 'pretending' to be User - and first question could be: "Should I go FPGA or ASCI" for my image-processing solution?"
Does the guideline explicitly refer to the handbook? To which part of the deliverable is it relevant (e.g., chapter of D1.2/D1.3)?
No. It should refer to Chapter 3 for the hardware overview and Chapter 2 for the particular challenges of embedded image processing (i.e., stringent power/performance demands and low time-to-market requires component reuse through IP cores).
Not really. The instantiation and evaluation sections are vague and need to be improved. See below for more detailed suggestions.
FC: This guideline was initial created before any REAL work had been done.. - shall improve with suggestions
- Guideline advice: Remove the discussion of CPU inside the FPGA as it is typically unnecessary when we have hard CPUs on chip.
FC: The point is/was that sometimes a 'soft-CPU' could be handy, even in something like a Zynq. Also, a 'bare-metal' FPGA could be used for an Image Processing solution and a 'soft-CPU' could be added. A FPGA could go to ASIC, if using a 'soft-CPU', like RISC-V, etc.
Also, remove the discussion of ASICs.
The key advice is to carefully select IP cores to minimise development time.
- Insights that led to the guideline: The first paragraph is good, but the second paragraph is imprecise. In particular, the statement "we have a CPU integrated into the FPGA" is incorrect. The Zynqs contain hard ARM cores and an FPGA fabric on the same chip. I suggest to remove the second paragraph since it is off message.
FC: Again, me thinking about 'generic' FPGAs with possible addition of a 'soft-CPU' to enable going to ASIC, if volume is BIG!
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Recommended implementation method of the guideline along with a solid motivation for the recommendation: This section is good.
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Instantiation of the recommended implementation method in the reference platform: Too vague. A list of steps to take to search for IP cores and evaluate their usefulness should be added.
- Evaluation of the guideline in reference applications: Too vague. Which IP cores did we use in the starter kit? What did we use them for? How did they perform? What did we learn?
FC: It seems like TUD has used an IP-Core [a problem!] - but initially, then Sundance ALSO used an IP-Core for the CameraLink efforts to convert image from camera to HDMI, but Synective design it out for FHG
- References and related guidelines: The author needs to check for related guideline and add links to them.
- 30/07/2018: Made some formatting changes in the guidelines to cope with template.
- 31/97/2018: Guideline reviewed.
- 22/11/2018: Author reviewed the review
TULIPP Guideline Wiki