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Review of Guideline #46

aripod edited this page Jan 11, 2019 · 5 revisions

Formatting

Item Outcome
Guideline complies with the Guideline-Template Yes
Name of guideline responsible with affiliation is clearly stated Yes

Is the audience of the guideline correctly specified?

We can add "System architect" as they have to deal with the whole system : clocking and power.

Is the expertise required to write the guideline correctly specified?

Yes

Are the keywords well selected?

Yes

Are parts of the guideline too generic or too specific?

The guideline is at a good level. It can be used in any project.

Does the guideline explicitly refer to the handbook? To which part of the deliverable is it relevant (e.g., chapter of D1.2/D1.3)?

No.

Does the guideline specify the work done in the project that can benefit from the guideline?

Not exactly. It says that the method could be used, but does not say it actually is.

Other comments

  1. Guideline advice: Replace 'should' be 'must' and 'done' by 'used': "Voltage scaling of the Processing System (PS) should not be done." As the following explains that it may damage the ARM A9 processors.

  2. Insights that led to the guideline: Just clarify where are the key features mentioned that led to write this guideline. I guess it comes from the Xilinx papers...

  3. Recommended implementation method of the guideline along with a solid motivation for the recommendation: Is there a reference that more explicitly explains what is the type and the cause of the problems we can get while doing power scaling with the ARM processors? Can you also give some more explanation of that? i.e. :

  • why is it not possible to power scale ARM A9 processors?
  • is it really not possible or just not advised?
  • if it is possible: then what should be taken care of prior to scale voltage?
  • what could be the problems? : is it damages that we may get?
  1. Instantiation of the recommended implementation method in the reference platform: The sentence is not clear: "The DVFS application is proposed for ZC702 FPGA board. Dynamic frequency scaling can be implemented on Tulipp board but for voltage scaling and power monitoring additional hardware on the Tulipp board is required." We do have a LynSyn board to monitor the power consumption and I don't think it is required to have addition hardware for voltage scaling, is it not?

  2. Evaluation of the guideline in reference applications: Is DVFS implemented in one of the applications? I know it is not implemented in the use cases, but if there is any test available on the forum, then we might say it is implemented on the platform and point to the forum part where the test is shared.

  3. References: A relevant list of reference is given.

Track changes:

  1. 19/10/2018: Guideline uploaded.
  2. 07/01/2019: guideline reviewed.
  3. 11/01/2019: Guideline updated.
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