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Turn off the FPGA device to save power if the latencies allow it
Item | Value |
---|---|
Guideline Number | 3 |
Guideline Responsible (Name, Affiliation) | Björn Gottschall, NTNU |
Guideline Reviewer (Name, Affiliation) | Timoteo García Bertoa, Sundance |
Guideline Audience (Category) | System architect |
Guideline Expertise (Category) | HW designers |
Guideline Keywords (Category) | Energy efficiency, FPGA |
Turning SRAM-based FPGA devices off can save a significant amount of energy, but adds latencies from the start-up process and required reconfiguration. To avoid depleting energy in batteries, the platform should be switched off for longer idle times.
It is traditional wisdom to turn off unused GPUs and CPUs to save power. However, this wisdom does not necessarily transfer to SRAM-based FPGA designs since they have to be reconfigured when powered on. Reconfiguration consumes extra power and adds additional latencies. The trade-offs are different for FPGAs that use non-volatile memory to store configuration data.
Recommended implementation method of the guideline along with a solid motivation for the recommendation
Measure the currents and power drawn when the FPGA device is powered on, being configured, in standby, and active. Include these measurements in system design and dynamic power management decisions.
Power-on current can be very high if the power-on sequencing is incorrect or the temperature is outside the recommended range. Configuration current can be higher than active power for low-power designs. SRAM-based FPGA devices draw current to restore configuration from non-volatile memory. Standby current is drawn all the time the device is powered on and active current when the device is active i.e., performing computation.
Not all vendors provide power measurement capability on-board. This is true for the for the EMC2DP, a predecessor for the reference platform. NTNU has constructed a general-purpose, fine-grained, high-frequency power monitoring device for the EMC2DP. This device will enable programmers to easily measure currents and power drawn when the FPGA device is powered on, being configured, in standby, and active.
Case | Power [W] | Time [mS] | Energy [J] |
---|---|---|---|
WFI | 4.95719 | 10000 | 49.5719 |
PL-SD | 5.05152 | 756.087 | 3.81939 |
PL | 5.20629 | 17.040 | 0.08872 |
Before comparing the energy consumption between idle and PL (Programmable Logic, FPGA) reconfiguration, it is required to define the idle state of the processing system (APU and/or RPU). Idle is considered a state from which the platform can wake up itself by any event. The least amount of energy is drawn by holding the processing system in the WFI (wait for interrupt) state as shown in the table above. Performing busy waiting or polling does consume more energy and is therefore not recommended as an idle state in an energy-critical environment.
Reconfiguration of the PL from a bitstream residing on the SD-Card takes 756 ms and consume 5.05 Watt as seen in the table (PL-SD), which is roughly 0.1 watts more than the idle state. Measurements of the PL reconfiguration from an in-memory prepared bitstream have shown that the limiting factor is the slow SD-Card interface. Only 2.3% of the energy required for reconfiguration from the SD-card is invested in the actual PL reconfiguration. Thus, using a faster interface than SDHC can save a reasonable amount of energy.
The measurements show that switching off the platform saves a significant amount of energy and that PL reconfiguration not only consumes slightly more energy than idling but is also a very fast process, depending on the interface used. However, temporarily switching off the platform adds latencies from the startup process that needs to be considered. Depending on the application and required reaction speeds the latencies added by PL reconfiguration alone could be negligible.
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