Instruction Set

Normative source: SPRU056D, chapter 6 (Assembly Language Instructions). Opcodes are additionally cross-checked against the toolchain's own instruction table (include/c5x_isa.h).

This page is the complete instruction set: it defines the notation, groups the instructions by function, and then gives one section for every instruction in alphabetical order. Jump straight to any mnemonic from the sidebar.

The toolchain's instruction table holds 229 entries: 228 are assembler mnemonics, counting every addressing variant and enhanced form, plus one internal format-group sentinel that is not a user instruction. A few mnemonics (for example ADD, AND, MPY, SUB) appear with a placeholder base opcode in the table and are resolved to a form-specific encoding by the assembler; the detail pages note this where it applies. The functional tables below list the primary instructions as the manual groups them.

How each instruction is documented

Every entry on the detail pages gives:

Field	Meaning
Syntax	the assembly forms (direct, indirect, short immediate, long immediate)
Operation	what the instruction computes, as a register-transfer expression
Operands	the legal value ranges for each operand
Opcode	the 16-bit encoding: fixed bits plus the named variable fields
Status bits	the ST0/ST1 bits that affect the instruction or that it changes
Words / Cycles	the instruction length in words and a representative cycle count
Example	a short, typical use

Operand notation (dma, ind, ARn, shift, pma, immediate #k and #lk) is defined on the Addressing Modes and Assembler Syntax pages.

Opcode field symbols

From SPRU056D Table 6-1, the symbols that appear in the Opcode field of the detail entries:

Symbol	Meaning
`AAAAAAA`	the 7 data-memory address bits; with `I=1` (indirect) these instead control the auxiliary-register update
`I`	addressing-mode bit: `I=0` direct, `I=1` indirect
`ARX`	3-bit auxiliary-register number for LAR and SAR
`BITX`	4-bit bit code selecting the bit tested by BIT
`CM`	2-bit compare selector for CMPR
`kkkkkkkk`	8-bit short-immediate constant (ADD, ADRK, LACL, LAR, RPT, SBRK, SUB)
`k kkkkkkkk`	9-bit short-immediate constant (LDP)
`k kkkkkkkk kkkk`	13-bit short-immediate constant (MPY)
`INTR#`	5-bit interrupt-vector number (0 to 31) for INTR
`PM`	2-bit product-shift mode written by SPM
`SHF`	3-bit shift for SACH and SACL
`SHFT`	4-bit shift for ADD, AND, BSAR, LACC, OR, SUB, XOR
`N`	1-bit count for XC (execute one or two instructions)
`TP`	2-bit condition for conditional execution (see below)
`ZLVC ZLVC`	two 4-bit fields: the conditions to test and their required states

The TP field encodes:

  TP     Condition
  00     BIO pin low
  01     TC = 1
  10     TC = 0  (NTC)
  11     none of the above

Functional groups

The manual sorts the instruction set into seven classes (SPRU056D Tables 6-4 through 6-10). Each instruction's full entry is on the alphabetical detail page for its first letter.

The map below colors the 256 possible high bytes (bits 15-8 of the instruction word) by the functional group that owns them, giving a one-glance picture of how the opcode space is carved up.

Opcode high-byte map, colored by functional group

Accumulator memory reference

Load, store, add, subtract, and the accumulator shifts and logicals that read or write data memory through the CALU.

ABS   ADCB  ADD   ADDB  ADDC  ADDS  ADDT  AND   ANDB  BSAR
CMPL  CRGT  CRLT  EXAR  LACB  LACC  LACL  LACT  LAMM  NEG
NORM  OR    ORB   ROL   ROLB  ROR   RORB  SACB  SACH  SACL
SAMM  SATH  SATL  SBB   SBBB  SFL   SFLB  SFR   SFRB  SUB
SUBB  SUBC  SUBS  SUBT  XOR   XORB  ZALR  ZAP

Auxiliary registers and data-page pointer

Load, store, modify and compare the auxiliary registers and set the data page.

ADRK  CMPR  LAR   LDP   MAR   SAR   SBRK

Parallel logic unit (PLU)

Read-modify-write logic on a data-memory word against an immediate or the DBMR.

AND   APL   CPL   LPH   LT    OPL   OR    SPLK  XPL

TREG, PREG and multiply

Load TREG, multiply, accumulate the product, and move or shift the product.

LTA   LTD   LTP   LTS   MAC   MACD  MADD  MADS  MPY   MPYA
MPYS  MPYU  PAC   SPAC  SPH   SPL   SPM   SQRA  SQRS  ZPR

Branch and call

Unconditional and conditional branches, calls, returns, and conditional execution.

B     BACC  BACCD BANZ  BANZD BCND  BCNDD BD    CALA  CALAD
CALL  CALLD CC    CCD   INTR  NMI   RET   RETC  RETCD RETD
RETE  RETI  TRAP  XC

I/O and data-memory operations

Block moves, table reads and writes, data moves, memory-mapped register moves, and port I/O.

BLDD  BLDP  BLPD  DMOV  IN    LMMR  OUT   SMMR  TBLR  TBLW

Control

Status-bit control, repeat setup, stack pushes and pops, bit tests, and the idle and no-operation instructions.

BIT   BITT  CLRC  IDLE  IDLE2 LST   NOP   POP   POPD  PSHD
PUSH  RPT   RPTB  RPTZ  SETC  SST

ABS

Absolute value of the accumulator.

Syntax: ABS

Operation: (PC) + 1 -> PC; |(ACC)| -> ACC; 0 -> C

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  0 |  0  0  0  0    = 0xBE00

Toolchain base 0xBE00 agrees with the manual graphic.

Status bits: Affected by OVM; not affected by SXM; affects C and OV. With OVM = 0 the ABS of 8000 0000h stays 8000 0000h; with OVM = 1 it becomes 7FFF FFFFh; OV is set in either case.

Words / Cycles: 1 word; 1 cycle for a single on-chip (DARAM) execution.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example:

    ABS                 ; ACC = FFFF FFFFh becomes 1h, C is cleared

ADCB

Add the accumulator buffer and carry to the accumulator.

Syntax: ADCB

Operation: (PC) + 1 -> PC; (ACC) + (ACCB) + (C) -> ACC

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  1 |  0  0  0  1    = 0xBE11

Toolchain base 0xBE11 agrees with the manual graphic.

Status bits: Affected by OVM; affects C and OV. C is set on a carry out of the addition, otherwise cleared. ACCB is left unchanged.

Words / Cycles: 1 word; 1 cycle (DARAM, single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example:

    ADCB                ; ACC = ACC + ACCB + C

ADD

Add a shifted data-memory value or an immediate constant to the accumulator.

This is the general ADD entry. The toolchain also exposes the individual forms as ADDH (shift of 16), ADDI (direct/indirect with shift), ADDK (short immediate), and ADLK (long immediate); each has its own section below.

Syntax:

    Direct:            ADD dma [,shift]
    Indirect:          ADD {ind} [,shift] [,ARn]
    Short immediate:   ADD #k
    Long immediate:    ADD #lk [,shift]

Operation:

Direct or indirect: (ACC) + ((dma) x 2^shift) -> ACC
Short immediate: (ACC) + k -> ACC
Long immediate: (ACC) + (lk x 2^shift) -> ACC

Operands: 0 <= dma <= 127; 0 <= shift <= 16 (defaults to 0); 0 <= n <= 7; 0 <= k <= 255; -32768 <= lk <= 32767.

Opcode: The manual gives one graphic per form:

 direct, with shift:        0 0 1 0  <-SHFT->  0  <----- dma ----->   = 0x2000
 indirect, with shift:      0 0 1 0  <-SHFT->  1  <- see Section 5.2  = 0x2080
 direct, shift of 16:       0 1 1 0  0 0 0 1   0  <----- dma ----->   = 0x6100
 indirect, shift of 16:     0 1 1 0  0 0 0 1   1  <- see Section 5.2  = 0x6180
 short immediate:           1 0 1 1  1 0 0 0   <--- 8-bit constant -> = 0xB800
 long immediate, w/ shift:  1 0 1 1  1 1 1 1   1 0 0 1  <-SHFT->      = 0xBF90
                            (second word = 16-bit constant)

The toolchain stores 0x0000 as the base for the umbrella mnemonic ADD; that value is a placeholder and does not match any single manual graphic, because the assembler resolves ADD to one of the form-specific encodings above (which the toolchain also names ADDI, ADDH, ADDK, ADLK).

Status bits: Affected by OVM and SXM (direct, indirect, long immediate) or OVM only (short immediate); affects C and OV. For a shift of 16 the C bit is set on carry but is not cleared when there is no carry, so a 32-bit accumulation produces a single correct carry.

Words / Cycles: 1 word (direct, indirect, short immediate) or 2 words (long immediate); 1 cycle for a single direct/indirect/short execution, 2 cycles for long immediate (DARAM). The short- and long-immediate forms are not repeatable.

Cycle class: IIA (ADD); I (ADD #k); III (ADD #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short and long immediate addressing modes, the ADD instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing):

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Single Instruction (long immediate addressing):

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example:

    ADD   DAT1,1        ; ACC += Data(DAT1) << 1  (DP = 6)
    ADD   #1111h,1      ; ACC += 1111h << 1  (long immediate)

ADDB

Add the accumulator buffer to the accumulator.

Syntax: ADDB

Operation: (PC) + 1 -> PC; (ACC) + (ACCB) -> ACC

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  1 |  0  0  0  0    = 0xBE10

Toolchain base 0xBE10 agrees with the manual graphic.

Status bits: Affected by OVM; affects C and OV. C is set on a carry, otherwise cleared. ACCB is left unchanged.

Words / Cycles: 1 word; 1 cycle (DARAM, single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example:

    ADDB                ; ACC = 1234h + ACCB(2h) = 1236h

ADDC

Add a data-memory value and the carry to the accumulator (sign extension suppressed).

Syntax:

    Direct:     ADDC dma
    Indirect:   ADDC {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + (dma) + (C) -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 1 0  0 0 0 0   0  <----- dma ----->      = 0x6000
 indirect:  0 1 1 0  0 0 0 0   1  <- see Section 5.2      = 0x6080

Toolchain base 0x6000 agrees with the manual direct graphic.

Status bits: Affected by OVM; not affected by SXM; affects C and OV. Useful in multiple-precision arithmetic.

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example:

    ADDC  DAT0          ; ACC += Data(DAT0) + C  (DP = 6)

ADDH

Add a data-memory value to the high half of the accumulator (shift of 16).

This is the shift-of-16 form of ADD; see ADD for the shared operation and status description.

Syntax:

    Direct:     ADD dma, 16
    Indirect:   ADD {ind}, 16 [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + ((dma) x 2^16) -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7.

Opcode:

 direct:    0 1 1 0  0 0 0 1   0  <----- dma ----->      = 0x6100
 indirect:  0 1 1 0  0 0 0 1   1  <- see Section 5.2      = 0x6180

Toolchain base 0x6100 agrees with the manual "shift of 16" graphic for ADD.

Status bits: Affected by OVM and SXM; affects C and OV. On a shift of 16 the C bit is set on carry but not cleared otherwise (see ADD).

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: see Instruction Timing.

Example:

    ADD   DAT1,16       ; ACC += Data(DAT1) << 16

ADDI

Add a shifted data-memory value to the accumulator (direct/indirect, shift 0-15).

This is the direct/indirect-with-shift form of ADD; see ADD for the shared operation and status description.

Syntax:

    Direct:     ADD dma [,shift]
    Indirect:   ADD {ind} [,shift] [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + ((dma) x 2^shift) -> ACC

Operands: 0 <= dma <= 127; 0 <= shift <= 16 (defaults to 0); 0 <= n <= 7.

Opcode:

 direct:    0 0 1 0  <-SHFT->  0  <----- dma ----->      = 0x2000
 indirect:  0 0 1 0  <-SHFT->  1  <- see Section 5.2      = 0x2080

Toolchain base 0x2000 agrees with the manual "direct addressing with shift" graphic for ADD.

Status bits: Affected by OVM and SXM; affects C and OV.

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: see Instruction Timing.

Example:

    ADD   *+,0,AR0      ; ACC += Data(*AR), no shift, then point ARP to AR0

ADDK

Add a short immediate constant to the accumulator.

This is the short-immediate form of ADD; see ADD for the shared operation and status description.

Syntax: ADD #k

Operation: (PC) + 1 -> PC; (ACC) + k -> ACC

Operands: 0 <= k <= 255 (an 8-bit positive constant).

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4  3  2  1  0
  1  0  1  1 |  1  0  0  0 |  <--- 8-bit constant --->     = 0xB800

Toolchain base 0xB800 agrees with the manual "short immediate" graphic for ADD.

Status bits: Affected by OVM; affects C and OV. The addition is unaffected by SXM, and no shift may be specified.

Words / Cycles: 1 word; 1 cycle (DARAM, single). Not repeatable.

Cycle class: see Instruction Timing.

Example:

    ADD   #1h           ; ACC = 2h + 1h = 3h

ADDS

Add an unsigned data-memory value to the accumulator (sign extension suppressed).

Syntax:

    Direct:     ADDS dma
    Indirect:   ADDS {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + (dma) -> ACC, where (dma) is treated as an unsigned 16-bit number.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 1 0  0 0 1 0   0  <----- dma ----->      = 0x6200
 indirect:  0 1 1 0  0 0 1 0   1  <- see Section 5.2      = 0x6280

Toolchain base 0x6200 agrees with the manual direct graphic.

Status bits: Affected by OVM; not affected by SXM; affects C and OV. Produces the same result as ADD with SXM cleared and a shift of 0.

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example:

    ADDS  DAT0          ; ACC = 0000 0003h + F006h = 0000 F009h  (DP = 6)

ADDT

Add a data-memory value shifted by TREG1 to the accumulator.

Syntax:

    Direct:     ADDT dma
    Indirect:   ADDT {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + ((dma) x 2^TREG1(3-0)) -> ACC. If SXM = 0 the dma is not sign-extended; if SXM = 1 it is.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 1 0  0 0 1 1   0  <----- dma ----->      = 0x6300
 indirect:  0 1 1 0  0 0 1 1   1  <- see Section 5.2      = 0x6380

Toolchain base 0x6300 agrees with the manual direct graphic.

Status bits: Affected by OVM, SXM, and TRM; affects C and OV. The shift count is the 4 LSBs of TREG1 (0 to 15 bits).

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example:

    ADDT  DAT127        ; ACC += Data(027Fh) << TREG1(3-0)  (DP = 4, SXM = 0)

ADLK

Add a long immediate constant (with shift) to the accumulator.

This is the long-immediate form of ADD; see ADD for the shared operation and status description.

Syntax: ADD #lk [,shift]

Operation: (PC) + 2 -> PC; (ACC) + (lk x 2^shift) -> ACC

Operands: -32768 <= lk <= 32767; 0 <= shift <= 16 (defaults to 0).

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  1 |  1  0  0  1 |  <-SHFT->      = 0xBF90
 (second word = 16-bit constant)

Toolchain base 0xBF90 agrees with the manual "long immediate with shift" graphic for ADD.

Status bits: Affected by OVM and SXM; affects C and OV.

Words / Cycles: 2 words; 2 cycles (DARAM, single). Not repeatable.

Cycle class: see Instruction Timing.

Example:

    ADD   #1111h,1      ; ACC += 1111h << 1 = 2222h added

ADRK

Add a short immediate constant to the current auxiliary register.

Syntax: ADRK #k

Operation: (PC) + 1 -> PC; (current AR) + 8-bit positive constant -> current AR

Operands: 0 <= k <= 255.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4  3  2  1  0
  0  1  1  1 |  1  0  0  0 |  <--- 8-bit constant --->     = 0x7800

Toolchain base 0x7800 agrees with the manual graphic.

Status bits: None affected. The add happens in the ARAU; all AR arithmetic is unsigned.

Words / Cycles: 1 word; 1 cycle (DARAM, single). Not repeatable.

Cycle class: I (ADRK #k) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The ADRK instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Example:

    ADRK  #80h          ; AR5 = 4321h becomes 43A1h

AND

Bitwise AND of a data-memory value or an immediate constant with the accumulator.

This is the general AND entry. The toolchain also exposes the forms as ANDI (direct/indirect) and ANDK (long immediate); each has its own section below.

Syntax:

    Direct:            AND dma
    Indirect:          AND {ind} [,ARn]
    Long immediate:    AND #lk [,shift]

Operation:

Direct or indirect: (ACC(15-0)) AND (dma) -> ACC(15-0); 0 -> ACC(31-16)
Long immediate: (ACC(30-0)) AND (lk x 2^shift) -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; lk: 16-bit constant; 0 <= shift <= 16.

Opcode: The manual gives one graphic per form:

 direct:                    0 1 1 0  1 1 1 0   0  <----- dma ----->   = 0x6E00
 indirect:                  0 1 1 0  1 1 1 0   1  <- see Section 5.2  = 0x6E80
 long immediate, w/ shift:  1 0 1 1  1 1 1 1   1 0 1 1  <-SHFT->      = 0xBFB0
 long immediate, shift 16:  1 0 1 1  1 1 1 0   1 0 0 0  0 0 1         = 0xBE81
                            (long immediate second word = 16-bit constant)

The toolchain stores 0x0000 as the base for the umbrella mnemonic AND; that value is a placeholder and does not match any single manual graphic, because the assembler resolves AND to one of the form-specific encodings above (also named ANDI and ANDK in the toolchain).

Status bits: Not affected by SXM (long immediate). No other status bits are listed as affected for the direct/indirect form.

Words / Cycles: 1 word (direct, indirect) or 2 words (long immediate); 1 cycle for a single direct/indirect execution, 2 cycles for long immediate (DARAM). The long-immediate form is not repeatable.

Cycle class: IIA (AND); III (AND #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the long immediate addressing modes, the AND instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block.

Cycles for a Repeat (RPT) Execution (direct or indirect addressing):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block.

Cycles for a Single Instruction (long immediate addressing):

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example:

    AND   DAT16         ; ACC = 1234 5678h AND 00FFh = 0000 0078h (DP = 4)
    AND   #00FFh,4      ; ACC = 1234 5678h AND (00FFh << 4) = 0000 0670h

ANDB

Bitwise AND of the accumulator buffer with the accumulator.

Syntax: ANDB

Operation: (PC) + 1 -> PC; (ACC) AND (ACCB) -> ACC

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  1 |  0  0  1  0    = 0xBE12

Toolchain base 0xBE12 agrees with the manual graphic.

Status bits: None affected. ACCB is left unchanged.

Words / Cycles: 1 word; 1 cycle (DARAM, single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example:

    ANDB                ; ACC = 0F0F FFFFh AND 5555 5555h = 0505 5555h

ANDI

Bitwise AND of a data-memory value with the accumulator low half (direct/indirect).

This is the direct/indirect form of AND; see AND for the shared operation and status description.

Syntax:

    Direct:     AND dma
    Indirect:   AND {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC(15-0)) AND (dma) -> ACC(15-0); 0 -> ACC(31-16)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 1 0  1 1 1 0   0  <----- dma ----->      = 0x6E00
 indirect:  0 1 1 0  1 1 1 0   1  <- see Section 5.2      = 0x6E80

Toolchain base 0x6E00 agrees with the manual direct graphic for AND.

Status bits: None listed as affected for this form.

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: see Instruction Timing.

Example:

    AND   *             ; ACC = 1234 5678h AND Data(*AR)(FF00h) = 0000 5600h

ANDK

Bitwise AND of a long immediate constant (with shift) with the accumulator.

This is the long-immediate form of AND; see AND for the shared operation and status description.

Syntax: AND #lk [,shift]

Operation: (PC) + 2 -> PC; (ACC(30-0)) AND (lk x 2^shift) -> ACC. The constant is shifted left and zero-extended on both ends.

Operands: lk: 16-bit constant; 0 <= shift <= 16.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  1 |  1  0  1  1 |  <-SHFT->      = 0xBFB0
 (second word = 16-bit constant)

Toolchain base 0xBFB0 agrees with the manual "long immediate with shift" graphic for AND.

Status bits: Not affected by SXM.

Words / Cycles: 2 words; 2 cycles (DARAM, single). Not repeatable.

Cycle class: see Instruction Timing.

Example:

    AND   #00FFh,4      ; ACC = 1234 5678h AND (00FFh << 4) = 0000 0670h

APAC

Add the shifted product register to the accumulator.

Syntax: APAC

Operation: (PC) + 1 -> PC; (ACC) + (shifted PREG) -> ACC

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  0 |  0  1  0  0    = 0xBE04

Toolchain base 0xBE04 agrees with the manual graphic.

Status bits: Affected by OVM and PM; not affected by SXM; affects C and OV. PREG is shifted per the PM bits and is always sign-extended. APAC is a subset of LTA, LTD, MAC, MACD, MADS, MADD, MPYA, and SQRA.

Words / Cycles: 1 word; 1 cycle (DARAM, single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example:

    APAC                ; (PM = 01) ACC = 20h + (PREG 40h << 1) = A0h

APL

AND a data-memory value with the DBMR or a long immediate constant, in place.

This is the general APL entry (a parallel logic unit instruction). The toolchain also exposes the forms as APLI (DBMR source, no long immediate) and APLK (long immediate specified); each has its own section below.

Syntax:

    Direct:     APL [#lk,] dma
    Indirect:   APL [#lk,] {ind} [,ARn]

Operation:

Long immediate not specified: (PC) + 1 -> PC; (dma) AND (DBMR) -> dma
Long immediate specified: (PC) + 2 -> PC; (dma) AND lk -> dma

The result is written back to the dma; the accumulator is unaffected.

Operands: 0 <= dma <= 127; lk: 16-bit constant; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode: The manual gives one graphic per form:

 direct, no long imm:     0 1 0 1  1 0 1 0   0  <----- dma ----->   = 0x5A00
 indirect, no long imm:   0 1 0 1  1 0 1 0   1  <- see Section 5.2  = 0x5A80
 direct, long imm:        0 1 0 1  1 1 1 0   0  <----- dma ----->   = 0x5E00
 indirect, long imm:      0 1 0 1  1 1 1 0   1  <- see Section 5.2  = 0x5E80
                          (long-immediate second word = 16-bit constant)

The toolchain stores 0x0003 as the base for the umbrella mnemonic APL; that value is a placeholder and does not match any single manual graphic, because the assembler resolves APL to one of the form-specific encodings above (also named APLI and APLK in the toolchain).

Status bits: Affects TC. The TC bit is set if the AND result is 0, otherwise cleared.

Words / Cycles: 1 word (no long immediate) or 2 words (long immediate specified); 1 cycle for a single DBMR-source DARAM execution, 2 cycles for the long-immediate form (DARAM).

Cycle class: V (APL); VI (APL) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction (second operand DBMR):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 3*	1+p
External	2+2d	2+2d	2+2d	5+2d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (second operand DBMR):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	2n-2	2n-2	2n-2, 2n+1*	2n-2+p
External	4n-2+2nd	4n-2+2nd	4n-2+2nd	4n+1+2nd+p

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	2	2	2	2+2p
SARAM	2	2	2	2+2p
External	3+2d	3+2d	3+2d	6+2d+2p

Cycles for a Repeat (RPT) Execution (long immediate specified):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n+1	n+1	n+1	n+1+2p
SARAM	2n-1	2n-1	2n-1, 2n+2*	2n-1+2p
External	4n-1+2nd	4n-1+2nd	4n-1+2nd	4n+2+2nd+2p

If the operand and the code reside in same SARAM block

Example:

    APL   DAT96         ; Data(60h) = 1111h AND DBMR(FF00h) = 1100h (DP = 0)
    APL   #0023h,DAT96  ; Data(60h) AND 0023h, in place (DP = 0)

APLI

AND a data-memory value with the DBMR, in place (no long immediate).

This is the DBMR-source form of APL; see APL for the shared operation and status description.

Syntax:

    Direct:     APL dma
    Indirect:   APL {ind} [,ARn]

Operation: (PC) + 1 -> PC; (dma) AND (DBMR) -> dma

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 0 1  1 0 1 0   0  <----- dma ----->      = 0x5A00
 indirect:  0 1 0 1  1 0 1 0   1  <- see Section 5.2      = 0x5A80

Toolchain base 0x5A00 agrees with the manual "long immediate not specified" direct graphic for APL.

Status bits: Affects TC (set if the AND result is 0).

Words / Cycles: 1 word; 1 cycle for a single DBMR-source DARAM execution.

Cycle class: see Instruction Timing.

Example:

    APL   *,AR7         ; Data(*AR6)(0EFFh) AND DBMR(0303h) = 0203h, ARP -> 7

APLK

AND a long immediate constant with a data-memory value, in place.

This is the long-immediate form of APL; see APL for the shared operation and status description.

Syntax:

    Direct:     APL #lk, dma
    Indirect:   APL #lk, {ind} [,ARn]

Operation: (PC) + 2 -> PC; (dma) AND lk -> dma

Operands: 0 <= dma <= 127; lk: 16-bit constant; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 0 1  1 1 1 0   0  <----- dma ----->      = 0x5E00
 indirect:  0 1 0 1  1 1 1 0   1  <- see Section 5.2      = 0x5E80
 (second word = 16-bit constant)

Toolchain base 0x5E00 agrees with the manual "long immediate specified" direct graphic for APL.

Status bits: Affects TC (set if the AND result is 0).

Words / Cycles: 2 words; 2 cycles (DARAM, single).

Cycle class: see Instruction Timing.

Example:

    APL   #0100h,*,AR6  ; Data(*AR5)(0FFFh) AND 0100h = 0100h, ARP -> 6

About the condition codes

Several instructions on this page take one or more condition codes and transfer control only when the tested condition(s) hold. SPRU056D lists the conditions in the BCND entry as:

Condition	Code	Condition	Code
ACC = 0	EQ	C = 0	NC
ACC != 0	NEQ	C = 1	C
ACC < 0	LT	OV = 0	NOV
ACC <= 0	LEQ	OV = 1	OV
ACC > 0	GT	TC = 0	NTC
ACC >= 0	GEQ	TC = 1	TC
BIO low	BIO	Unconditionally	UNC

Not all combinations are meaningful, and testing BIO is mutually exclusive with testing TC. The exact TP and ZLVC field encodings for these conditions live in SPRU056D Table 6-1 (page 6-2), which is outside the provided source range; this page therefore does not decode those bit fields. See also the Program Control page.

The single-condition branch mnemonics BBNZ, BBZ, BC, BGEZ, BGZ, BIOZ, BLEZ, BLZ, BNC, BNV, BNZ, BV, and BZ are not given individual entries in the provided source range; SPRU056D documents their behavior through the general BCND entry. Each is a branch that tests exactly one condition. The condition named in each section below is the conventional meaning of the mnemonic; the base opcodes come from the toolchain table (source 2) and all share the BCND opcode-family prefix (bits 15-10 = 111000).

B

Unconditional branch to a program-memory address, with an optional AR/ARP update.

Syntax: B pma [, {ind} [,ARn ] ]

Operation: pma -> PC; modify current AR and ARP as specified.

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 0 0 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7980   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles (single execution, ROM/DARAM/SARAM). Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The B instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
4	4	4	4+4p [a]

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: B 191,*+,AR1 - load 191 into the PC, increment the current AR, set ARP = 1.

BACC

Unconditional branch to the address held in the accumulator low word.

Syntax: BACC

Operation: ACC(15-0) -> PC.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 1 0 0 0 0 0
base: 0xBE20   FMT 0x00

Status bits: None affected.

Words / Cycles: 1 word; 4 cycles (single execution). Not repeatable.

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BACC instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
4	4	4	4+3p [a]

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: BACC - with ACC = 191, continue execution from location 191.

BACCD

Delayed branch to the address held in the accumulator low word; the following instruction word(s) execute before the branch is taken.

Syntax: BACCD

Operation: ACC(15-0) -> PC (after the delay slot executes).

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 1 0 0 0 0 1
base: 0xBE21   FMT 0x00

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single execution). Not repeatable.

Cycle class: XI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BACCD instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
2	2	2	2+p

Example: BACCD then MAR *+,AR1 / LDP #5 - the two following words execute, then control passes to the ACC address.

BANZ

Branch on auxiliary register not zero (loop control); the current AR is decremented by default.

Syntax: BANZ pma [, {ind} [,ARn ] ]

Operation: if (current AR) != 0: pma -> PC; else (PC) + 2 -> PC. Modify current AR as specified.

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 0 1 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7B80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles if the branch is taken, 2 if not. Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BANZ instruction is not repeatable.

Cycles for a Single Instruction:

Condition	ROM	DARAM	SARAM	External Memory
True	4	4	4	4+4p [a]
False	2	2	2	2+2p

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: BANZ PGM191,AR0 - loop back to PGM191 while AR0 != 0, then fall through.

BANZD

Delayed branch on auxiliary register not zero; the following instruction word(s) execute before the branch is taken.

Syntax: BANZD pma [, {ind} [,ARn ] ]

Operation: if (current AR) != 0: pma -> PC; else (PC) + 2 -> PC. Modify current AR as specified (after the delay slot).

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 1 1 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7F80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BANZD instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: BANZD PGM0 then LACC #01h / LDP #5 - the delay-slot words execute, then branch if the current AR is nonzero.

BBNZ

Branch if the TC (test/control) bit is set. Not individually documented in the source range; a single-condition form of BCND (see "About the condition codes").

Syntax: BBNZ pma (as a one-condition BCND; see BCND).

Operation: if (TC set): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE100  (1110 0001 0000 0000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BBNZ PGM191 - branch when TC = 1.

BBZ

Branch if the TC (test/control) bit is cleared. Not individually documented in the source range; a single-condition form of BCND.

Syntax: BBZ pma (as a one-condition BCND; see BCND).

Operation: if (TC cleared): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE200  (1110 0010 0000 0000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BBZ PGM191 - branch when TC = 0.

BC

Branch if carry: the C bit is set. Not individually documented in the source range; a single-condition form of BCND.

Syntax: BC pma (equivalent to BCND pma,C; see BCND).

Operation: if (C = 1): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE311  (1110 0011 0001 0001)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BC PGM191 - branch when C = 1.

BCND

Conditional branch: transfer control to pma when the specified condition(s) are met.

Syntax: BCND pma, cond [,cond1 ] [,...]

Operation: if (condition(s)): pma -> PC; else (PC) + 2 -> PC.

Operands: 0 <= pma <= 65535; conditions as listed in "About the condition codes".

Opcode:

word 1:  15..10 = 1 1 1 0 0 0   bits9-8 = TP   bits7-4 = ZLVC   bits3-0 = ZLVC  (see Table 6-1)
word 2:  16-bit pma constant
base: 0xE300   FMT 0x18

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles if the branch is taken, 2 if not. Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BCND instruction is not repeatable.

Cycles for a Single Instruction:

Condition	ROM	DARAM	SARAM	External Memory
True	4	4	4	4+4p [a]
False	2	2	2	2+2p

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: BCND PGM191,LEQ,C - branch to 191 if ACC <= 0 and C = 1.

BCNDD

Delayed conditional branch; the following instruction word(s) execute before the branch is taken and do not affect the tested conditions.

Syntax: BCNDD pma, cond [,cond1 ] [,...]

Operation: if (condition(s)): pma -> PC; else (PC) + 2 -> PC (after the delay slot).

Operands: 0 <= pma <= 65535; conditions as listed in "About the condition codes".

Opcode:

word 1:  15..10 = 1 1 1 1 0 0   bits9-8 = TP   bits7-4 = ZLVC   bits3-0 = ZLVC  (see Table 6-1)
word 2:  16-bit pma constant
base: 0xF300   FMT 0x18

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BCNDD instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: BCNDD PGM191,OV then MAR *,AR1 / LDP #5 - delay-slot words execute, then branch if OV is set.

BD

Delayed unconditional branch; the following instruction word(s) execute before the branch is taken.

Syntax: BD pma [, {ind} [,ARn ] ]

Operation: pma -> PC; modify current AR and ARP as specified (after the delay slot).

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 1 0 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7D80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BD instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: BD 191 then MAR *+,AR1 / LDP #5 - delay-slot words execute, then control passes to 191.

BDDD

Block move data-to-data, destination pointer in BMAR, direct addressing. Not a separate entry in the source range; this is the direct, destination-by-BMAR variant of BLDD (see BLDD). Its base opcode 0xAD00 matches the BLDD "DEST by BMAR, direct" encoding in the BLDD opcode graphic.

Syntax: BLDD dma, BMAR (this variant; see BLDD).

Operation: (dma) -> (dst addressed by BMAR); see BLDD for the full RPT sequence.

Operands: 0 <= dma <= 127.

Opcode:

15..8 = 1 0 1 0 1 1 0 1   bit7 = 0 (direct)   bits6-0 = dma
base: 0xAD00   FMT 0x01

Status bits: None affected (as BLDD).

Words / Cycles: 1 word; 2 cycles (single execution, representative; as BLDD with a BMAR pointer).

Cycle class: see Instruction Timing.

Example: BLDD 00h,BMAR - copy Data(dma) to the location addressed by BMAR.

BDSD

Block move data-to-data, source pointer in BMAR, direct addressing. Not a separate entry in the source range; this is the direct, source-by-BMAR variant of BLDD (see BLDD). Its base opcode 0xAC00 matches the BLDD "SRC by BMAR, direct" encoding.

Syntax: BLDD BMAR, dma (this variant; see BLDD).

Operation: (src addressed by BMAR) -> (dma); see BLDD for the full RPT sequence.

Operands: 0 <= dma <= 127.

Opcode:

15..8 = 1 0 1 0 1 1 0 0   bit7 = 0 (direct)   bits6-0 = dma
base: 0xAC00   FMT 0x01

Status bits: None affected (as BLDD).

Words / Cycles: 1 word; 2 cycles (single execution, representative; as BLDD with a BMAR pointer).

Cycle class: see Instruction Timing.

Example: BLDD BMAR,20h - copy the BMAR-addressed word to Data(dma).

BGEZ

Branch if accumulator greater than or equal to zero (GEQ). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BGEZ pma (equivalent to BCND pma,GEQ; see BCND).

Operation: if (ACC >= 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE38C  (1110 0011 1000 1100)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BGEZ PGM191 - branch when ACC >= 0.

BGZ

Branch if accumulator greater than zero (GT). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BGZ pma (equivalent to BCND pma,GT; see BCND).

Operation: if (ACC > 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE304  (1110 0011 0000 0100)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BGZ PGM191 - branch when ACC > 0.

BIOZ

Branch if the BIO pin is low. Not individually documented in the source range; a single-condition form of BCND (BIO condition).

Syntax: BIOZ pma (equivalent to BCND pma,BIO; see BCND).

Operation: if (BIO low): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE000  (1110 0000 0000 0000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BIOZ PGM191 - branch when the BIO pin is low.

BIT

Copy a fixed bit of a data-memory word to the TC status bit.

Syntax:

Direct: BIT dma, bit code
Indirect: BIT {ind} , bit code [,ARn ]

Operation: (PC) + 1 -> PC; (dma bit at bit address (15 - bit code)) -> TC.

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= bit code <= 15; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

Direct:    15..12 = 0 1 0 0   bits11-8 = BITX (see Table 6-1)   bit7 = 0   bits6-0 = dma
Indirect:  15..12 = 0 1 0 0   bits11-8 = BITX                   bit7 = 1   bits6-0 = AR-update fields
base: 0x4000   FMT 0x0e

Status bits: Affects TC.

Words / Cycles: 1 word; 1 cycle (single execution, on-chip operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Example: BIT 0h,15 - copy the LSB of the addressed word into TC.

BITT

Copy a bit of a data-memory word, selected by the four LSBs of TREG2, to the TC status bit.

Syntax:

Direct: BITT dma
Indirect: BITT {ind} [,ARn ]

Operation: (PC) + 1 -> PC; (dma bit at bit address (15 - TREG2(3-0))) -> TC.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

Direct:    15..8 = 0 1 1 0 1 1 1 1   bit7 = 0   bits6-0 = dma
Indirect:  15..8 = 0 1 1 0 1 1 1 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
base: 0x6F00   FMT 0x01

Status bits: Affects TC.

Words / Cycles: 1 word; 1 cycle (single execution, on-chip operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Example: BITT 00h - test the bit of Data(dma) selected by TREG2(3-0) and copy it to TC.

BKDK

Block move data-to-data, destination pointer by long immediate, direct addressing. Not a separate entry in the source range; this is the direct, destination-by-long-immediate variant of BLDD (see BLDD). Its base opcode 0xA900 matches the BLDD "DEST by long immediate, direct" encoding.

Syntax: BLDD dma, #addr (this variant; see BLDD).

Operation: (dma) -> (dst addressed by #addr); see BLDD for the full RPT sequence.

Operands: 0 <= dma <= 127; 0 <= addr <= 65535.

Opcode:

15..8 = 1 0 1 0 1 0 0 1   bit7 = 0 (direct)   bits6-0 = dma
word 2: 16-bit addr constant
base: 0xA900   FMT 0x11

Status bits: None affected (as BLDD).

Words / Cycles: 2 words; 3 cycles (single execution, representative; as BLDD with a long-immediate pointer).

Cycle class: see Instruction Timing.

Example: BLDD 00h,#321h - copy Data(dma) to data location 321h.

BLDD

Block move within data memory: copy the word at the source dma to the destination dma. Source and/or destination may be pointed to by a long immediate value, by BMAR, or by a dma. Usable with RPT for multi-word moves.

Syntax (valid cases):

BLDD BMAR, dma / BLDD BMAR, {ind} [,ARn ]
BLDD dma, BMAR / BLDD {ind}, BMAR [,ARn ]
BLDD #addr, dma / BLDD #addr, {ind} [,ARn ]
BLDD dma, #addr / BLDD {ind}, #addr [,ARn ]

Operation: copy (src addressed by PFC) -> dst, iterated under the repeat counter; PFC sourced from BMAR or the long immediate; (PFC)+1 each pass; MCS save/restore around the move.

Operands: 0 <= addr <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

SRC by BMAR:            15..8 = 1 0 1 0 1 1 0 0   bit7 = 0 direct (dma) / 1 indirect   -> 0xAC00 / 0xAC80
DEST by BMAR:           15..8 = 1 0 1 0 1 1 0 1   bit7 = 0 / 1                         -> 0xAD00 / 0xAD80
SRC by long immediate:  15..8 = 1 0 1 0 1 0 0 0   bit7 = 0 / 1   word2 = 16-bit const  -> 0xA800 / 0xA880
DEST by long immediate: 15..8 = 1 0 1 0 1 0 0 1   bit7 = 0 / 1   word2 = 16-bit const  -> 0xA900 / 0xA980
toolchain base: 0x0000   FMT 0x21

Opcode disagreement: the toolchain base 0x0000 (FMT 0x21) is a pseudo-base; it matches no encoding in the manual graphic. The real encodings above are carried by the FMT-0x21 expansion and by the toolchain's variant mnemonics BDSD (0xAC00), BDDD (0xAD00), BLKD (0xA800), and BKDK (0xA900).

Status bits: None affected.

Words / Cycles: 1 word when a pointer is BMAR, 2 words when a pointer is a long immediate; 2 cycles (BMAR form) or 3 cycles (long-immediate form), DARAM-to-DARAM single execution. With RPT it becomes effectively single-cycle per word once the pipeline is primed.

Cycle class: XIII (BLDD); XII (BLDD) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction (SRC or DEST in BMAR):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM / Destination: DARAM	2	2	2	2+p
Source: SARAM / Destination: DARAM	2	2	2	2+p
Source: External / Destination: DARAM	2+dsrc	2+dsrc	2+dsrc	2+dsrc+p
Source: DARAM / Destination: SARAM	2	2	2, 3 [a]	2+p
Source: SARAM / Destination: SARAM	2	2	2, 3 [a]	2+p
Source: External / Destination: SARAM	2+dsrc	2+dsrc	2+dsrc, 3+dsrc [a]	2+dsrc+p
Source: DARAM / Destination: External	3+ddst	3+ddst	3+ddst	5+ddst+p
Source: SARAM / Destination: External	3+ddst	3+ddst	3+ddst	5+ddst+p
Source: External / Destination: External	3+dsrc+ddst	3+dsrc+ddst	3+dsrc+ddst	5+dsrc+ddst+p

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC or DEST in BMAR):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM / Destination: DARAM	n+1	n+1	n+1	n+1+p
Source: SARAM / Destination: DARAM	n+1	n+1	n+1	n+1+p
Source: External / Destination: DARAM	n+1+ndsrc	n+1+ndsrc	n+1+ndsrc	n+1+ndsrc+p
Source: DARAM / Destination: SARAM	n+1	n+1	n+1, n+3 [a]	n+1+p
Source: SARAM / Destination: SARAM	n+1, 2n-1 [b]	n+1, 2n-1 [b]	n+1, 2n-1 [b], n+3 [c], 2n+1 [c]	n+1+p, 2n-1+p [b]
Source: External / Destination: SARAM	n+1+ndsrc [a]	n+1+ndsrc	n+1+ndsrc, n+3+ndsrc [a]	n+1+ndsrc+p
Source: DARAM / Destination: External	2n+1+nddst	2n+1+nddst	2n+1+nddst	2n+1+nddst+p
Source: SARAM / Destination: External	2n+1+nddst	2n+1+nddst	2n+1+nddst	2n+1+nddst+p
Source: External / Destination: External	4n-1+ndsrc+nddst	4n-1+ndsrc+nddst	4n-1+ndsrc+nddst	4n+1+ndsrc+nddst+p

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block

Cycles for a Single Instruction (SRC or DEST long immediate):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM / Destination: DARAM	3	3	3	3+2p
Source: SARAM / Destination: DARAM	3	3	3	3+2p
Source: External / Destination: DARAM	3+dsrc	3+dsrc	3+dsrc	3+dsrc+2p
Source: DARAM / Destination: SARAM	3	3	3, 4 [a]	3+2p
Source: SARAM / Destination: SARAM	3	3	3, 4 [a]	3+2p

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Single Instruction (SRC or DEST long immediate) (Continued):

Operand	ROM	DARAM	SARAM	External Memory
Source: External / Destination: SARAM	3+dsrc	3+dsrc	3+dsrc, 4+dsrc	3+dsrc+2p
Source: DARAM / Destination: External	4+ddst	4+ddst	4+ddst	6+ddst+2p
Source: SARAM / Destination: External	4+ddst	4+ddst	4+ddst	6+ddst+2p
Source: External / Destination: External	4+dsrc+ddst	4+dsrc+ddst	4+dsrc+ddst	6+dsrc+ddst+2p
Source: DARAM / Destination: DARAM	n+2	n+2	n+2	n+2+2p

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC or DEST long immediate):

Operand	ROM	DARAM	SARAM	External Memory
Source: SARAM / Destination: DARAM	n+2	n+2	n+2	n+2+2p
Source: External / Destination: DARAM	n+2+ndsrc	n+2+ndsrc	n+2+ndsrc	n+2+ndsrc
Source: DARAM / Destination: SARAM	n+2	n+2	n+2, n+4 [a]	n+2+2p
Source: SARAM / Destination: SARAM	n+2, 2n [b]	n+2, 2n [b]	n+2, 2n [b], n+4 [a], 2n+2 [c]	n+2+2p, 2n+2p [b]
Source: External / Destination: SARAM	n+2ndsrc	n+2ndsrc	n+2ndsrc, n+4+ndsrc [a]	n+2+ndsrc+2p
Source: DARAM / Destination: External	2n+2+nddst	2n+2+nddst	2n+2+nddst	2n+2+nddst+2p
Source: SARAM / Destination: External	2n+2+nddst	2n+2+nddst	2n+2+nddst	2n+2+nddst+2p
Source: External / Destination: External	4n+ndsrc+nddst [b]	4n+ndsrc+nddst	4n+ndsrc+nddst	4n+2+ndsrc+nddst+2p

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block

Example: BLDD #300h,20h - copy data memory 300h into the dma 20h.

BLDP

Block move from data memory to program memory; the destination pma is pointed to by BMAR. Usable with RPT.

Syntax:

Direct: BLDP dma
Indirect: BLDP {ind} [,ARn ]

Operation: (PC)+1 -> PC; (PFC) -> MCS; (BMAR) -> PFC; then copy (dma) -> (dst addressed by PFC), iterated under the repeat counter with (PFC)+1 each pass; (MCS) -> PFC.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

Direct:    15..8 = 0 1 0 1 0 1 1 1   bit7 = 0   bits6-0 = dma
Indirect:  15..8 = 0 1 0 1 0 1 1 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
base: 0x5700   FMT 0x01

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single execution, DARAM-to-DARAM). Single-cycle per word under RPT once primed.

Cycle class: XVI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM / Destination: DARAM	2	2	2	2+p
Source: SARAM / Destination: DARAM	2	2, 3 [d]	2	2+p
Source: External / Destination: DARAM	2+dsrc	2+dsrc	2+dsrc	3+dsrc+pcode
Source: DARAM / Destination: SARAM	2	2	2, 3 [a]	2+p
Source: SARAM / Destination: SARAM	2	2	2, 3 [a] [d], 4 [c]	2+p
Source: External / Destination: SARAM	2+dsrc	2+dsrc	2+dsrc, 3+dsrc [a]	3+dsrc+pcode
Source: DARAM / Destination: External	3+pdst	3+pdst	3+pdst	4+pdst+pcode
Source: SARAM / Destination: External	3+pdst	3+pdst	3+pdst, 4+pdst [d]	4+pdst+pcode
Source: External / Destination: External	3+dsrc+pdst	3+dsrc+pdst	3+dsrc+pdst	5+dsrc+pdst+pcode

[a] If the destination operand and the code are in the same SARAM block [c] If both operands and the code are in the same SARAM block [d] If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM / Destination: DARAM	n+1	n+1	n+1	n+1+pcode
Source: SARAM / Destination: DARAM	n+1	n+1	n+1, n+2 [d]	n+1+pcode
Source: External / Destination: DARAM	n+1+ndsrc	n+1+ndsrc	n+1+ndsrc	n+2+ndsrc+pcode

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block [d] If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (Continued):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM / Destination: SARAM	n+1	n+1	n+1, n+2 [a]	n+1+pcode
Source: SARAM / Destination: SARAM	n+1, 2n-1 [b]	n+1, 2n-1 [b]	n+1, 2n-1 [b], n+2 [a] [d], 2n+1 [c]	n+1+pcode, 2n-1+pcode [b]
Source: External / Destination: SARAM	n+1+ndsrc	n+1+ndsrc	n+1+ndsrc, n+2+npsrc [a]	n+2+ndsrc+pcode
Source: DARAM / Destination: External	2n+1+npdst	2n+1+npdst	2n+1+npdst	2n+2+npdst+pcode
Source: SARAM / Destination: External	2n+1+npdst	2n+1+npdst	2n+1+npdst, 2n+2+npdst [d]	2n+2+npdst+pcode
Source: External / Destination: External	4n-1+ndsrc+npdst	4n-1+ndsr+npdst	4n-1+ndsrc+npdst	4n+1+ndsrc+npdst+pcode

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block [d] If the source operand and the code are in the same SARAM block

Example: BLDP 00h - copy Data(dma) to the program location addressed by BMAR.

BLEZ

Branch if accumulator less than or equal to zero (LEQ). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BLEZ pma (equivalent to BCND pma,LEQ; see BCND).

Operation: if (ACC <= 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE3CC  (1110 0011 1100 1100)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BLEZ PGM191 - branch when ACC <= 0.

BLKD

Block move data-to-data, source pointer by long immediate, direct addressing. Not a separate entry in the source range; this is the direct, source-by-long-immediate variant of BLDD (see BLDD). Its base opcode 0xA800 matches the BLDD "SRC by long immediate, direct" encoding.

Syntax: BLDD #addr, dma (this variant; see BLDD).

Operation: (src addressed by #addr) -> (dma); see BLDD for the full RPT sequence.

Operands: 0 <= dma <= 127; 0 <= addr <= 65535.

Opcode:

15..8 = 1 0 1 0 1 0 0 0   bit7 = 0 (direct)   bits6-0 = dma
word 2: 16-bit addr constant
base: 0xA800   FMT 0x11

Status bits: None affected (as BLDD).

Words / Cycles: 2 words; 3 cycles (single execution, representative; as BLDD with a long-immediate pointer).

Cycle class: see Instruction Timing.

Example: BLDD #300h,20h - copy data location 300h to the dma 20h.

BLKP

Block move program-to-data, source pointer by long immediate, direct addressing. Not a separate entry in the source range; this is the direct, source-by-long-immediate variant of BLPD (see BLPD). Its base opcode 0xA500 matches the BLPD "SRC by long immediate, direct" encoding.

Syntax: BLPD #pma, dma (this variant; see BLPD).

Operation: (pma addressed by #pma) -> (dma); see BLPD for the full RPT sequence.

Operands: 0 <= pma <= 65535; 0 <= dma <= 127.

Opcode:

15..8 = 1 0 1 0 0 1 0 1   bit7 = 0 (direct)   bits6-0 = dma
word 2: 16-bit pma constant
base: 0xA500   FMT 0x11

Status bits: None affected (as BLPD).

Words / Cycles: 2 words; 3 cycles (single execution, representative; as BLPD with a long-immediate source).

Cycle class: see Instruction Timing.

Example: BLPD #800h,00h - copy program location 800h into the dma.

BLPD

Block move from program memory to data memory. The source pma is pointed to by a long immediate value or by BMAR; the destination is a dma or the current AR. Usable with RPT.

Syntax (valid cases):

BLPD BMAR, dma / BLPD BMAR, {ind} [,ARn ]
BLPD #pma, dma / BLPD #pma, {ind} [,ARn ]

Operation: PFC sourced from the long immediate or BMAR (with (PFC) -> MCS saved first); copy (pma addressed by PFC) -> dst, iterated under the repeat counter with (PFC)+1 each pass; (MCS) -> PFC.

Operands: 0 <= pma <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

SRC by BMAR:            15..8 = 1 0 1 0 0 1 0 0   bit7 = 0 direct (dma) / 1 indirect   -> 0xA400 / 0xA480
SRC by long immediate:  15..8 = 1 0 1 0 0 1 0 1   bit7 = 0 / 1   word2 = 16-bit const  -> 0xA500 / 0xA580
toolchain base: 0x0001   FMT 0x21

Opcode disagreement: the toolchain base 0x0001 (FMT 0x21) is a pseudo-base; it matches no encoding in the manual graphic. The real encodings above are carried by the FMT-0x21 expansion and by the toolchain's variant mnemonics BPSD (0xA400) and BLKP (0xA500).

Status bits: None affected.

Words / Cycles: 1 word when the source is BMAR, 2 words when the source is a long immediate; 2 cycles (BMAR form) or 3 cycles (long-immediate form), DARAM/ROM-to-DARAM single execution. Single-cycle per word under RPT once primed.

Cycle class: XV (BLPD); XIV (BLPD) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction (SRC in BMAR):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM/ROM / Destination: DARAM	2	2	2	2+pcode
Source: SARAM / Destination: DARAM	2	2	2	2+pcode
Source: External / Destination: DARAM	2+psrc	2+psrc	2+psrc	2+psrc+pcode

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Single Instruction (SRC in BMAR) (Continued):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM/ROM / Destination: SARAM	2	2	2, 3 [a]	2+pcode
Source: SARAM / Destination: SARAM	2	2	2, 3 [a]	2+pcode
Source: External / Destination: SARAM	2+psrc	2+psrc	2+psrc, 3+psrc [a]	2+psrc+2pcode
Source: DARAM/ROM / Destination: External	3+ddst	3+ddst	3+ddst	5+ddst+pcode
Source: SARAM / Destination: External	3+ddst	3+ddst	3+ddst	5+ddst+pcode
Source: External / Destination: External	3+psrc+ddst	3+psrc+ddst	3+psrc+ddst	5+psrc+ddst+pcode

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC in BMAR):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM/ROM / Destination: DARAM	n+1	n+1	n+1	n+1+pcode
Source: SARAM / Destination: DARAM	n+1	n+1	n+1	n+1+pcode
Source: External / Destination: DARAM	n+1+npsrc	n+1+npsrc	n+1+npsrc	n+1+npsrc+pcode
Source: DARAM/ROM / Destination: SARAM	n+1	n+1	n+1, n+3 [a]	n+1+pcode
Source: SARAM / Destination: SARAM	n+1, 2n-1 [b]	n+1, 2n-1 [b]	n+1, 2n-1 [b], n+3 [a], 2n+1 [c]	n+1+pcode, 2n-1+pcode [b]
Source: External / Destination: SARAM	n+1+npsrc	n+1+npsrc	n+1+npsrc, n+3+npsrc [a]	n+1+npsrc+pcode
Source: DARAM/ROM / Destination: External	2n+1+nddst	2n+1+nddst	2n+1+nddst	2n+1+nddst+pcode
Source: SARAM / Destination: External	2n+1+nddst	2n+1+nddst	2n+1+nddst	2n+1+nddst+pcode
Source: External / Destination: External	4n-1+npsrc+nddst	4n-1+npsrc+nddst	4n-1+npsrc+nddst	4n+1+npsrc+nddst+pcode

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block

Cycles for a Single Instruction (SRC long immediate):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM/ROM / Destination: DARAM	3	3	3	3+2pcode
Source: SARAM / Destination: DARAM	3	3	3	3+2pcode
Source: External / Destination: DARAM	3+psrc	3+psrc	3+psrc	3+psrc+2pcode
Source: DARAM/ROM / Destination: SARAM	3	3	3, 4 [a]	3+2pcode
Source: SARAM / Destination: SARAM	3	3	3, 4 [a]	3+2pcode

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Single Instruction (SRC long immediate) (Continued):

Operand	ROM	DARAM	SARAM	External Memory
Source: External / Destination: SARAM	3+psrc	3+psrc	3+psrc, 4+psrc [a]	3+psrc+2pcode
Source: DARAM/ROM / Destination: External	4+ddst	4+ddst	4+ddst	6+ddst+2pcode
Source: SARAM / Destination: External	4+ddst	4+ddst	4+ddst	6+ddst+2pcode
Source: External / Destination: External	4+psrc+ddst	4+psrc+ddst	4+psrc+ddst	6+psrc+ddst+2pcode

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC long immediate):

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM/ROM / Destination: DARAM	n+2	n+2	n+2	n+2+2pcode
Source: SARAM / Destination: DARAM	n+2	n+2	n+2	n+2+2pcode
Source: External / Destination: DARAM	n+2+npsrc	n+2+npsrc	n+2+npsrc	n+2+npsrc+2pcode
Source: DARAM/ROM / Destination: SARAM	n+2	n+2	n+2, n+4 [a]	n+2+2pcode
Source: SARAM / Destination: SARAM	n+2, 2n [b]	n+2, 2n [b]	n+2, 2n [b], n+4 [a], 2n+2 [c]	n+2+2pcode, 2n+2pcode [b]
Source: External / Destination: SARAM	n+2+npsrc [a]	n+2+npsrc	n+2+npsrc, n+4+npsrc [a]	n+2+npsrc+2pcode
Source: DARAM/ROM / Destination: External	2n+2+nddst	2n+2+nddst	2n+2+nddst	2n+2+nddst+2pcode
Source: SARAM / Destination: External	2n+2+nddst	2n+2+nddst	2n+2+nddst	2n+2+nddst+2pcode
Source: External / Destination: External	4n+npsrc+nddst [a]	4n+npsrc+nddst	4n+npsrc+nddst	4n+2+npsrc+nddst+2pcode

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block

Example: BLPD BMAR,00h - copy the BMAR-addressed program word into the dma.

BLZ

Branch if accumulator less than zero (LT). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BLZ pma (equivalent to BCND pma,LT; see BCND).

Operation: if (ACC < 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE344  (1110 0011 0100 0100)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BLZ PGM191 - branch when ACC < 0.

BNC

Branch if no carry: the C bit is cleared. Not individually documented in the source range; a single-condition form of BCND.

Syntax: BNC pma (equivalent to BCND pma,NC; see BCND).

Operation: if (C = 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE301  (1110 0011 0000 0001)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BNC PGM191 - branch when C = 0.

BNV

Branch if no overflow: the OV bit is cleared. Not individually documented in the source range; a single-condition form of BCND.

Syntax: BNV pma (equivalent to BCND pma,NOV; see BCND).

Operation: if (OV = 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE302  (1110 0011 0000 0010)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BNV PGM191 - branch when OV = 0.

BNZ

Branch if accumulator not zero (NEQ). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BNZ pma (equivalent to BCND pma,NEQ; see BCND).

Operation: if (ACC != 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE308  (1110 0011 0000 1000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BNZ PGM191 - branch when ACC != 0.

BPSD

Block move program-to-data, source pointer in BMAR, direct addressing. Not a separate entry in the source range; this is the direct, source-by-BMAR variant of BLPD (see BLPD). Its base opcode 0xA400 matches the BLPD "SRC by BMAR, direct" encoding.

Syntax: BLPD BMAR, dma (this variant; see BLPD).

Operation: (pma addressed by BMAR) -> (dma); see BLPD for the full RPT sequence.

Operands: 0 <= dma <= 127.

Opcode:

15..8 = 1 0 1 0 0 1 0 0   bit7 = 0 (direct)   bits6-0 = dma
base: 0xA400   FMT 0x01

Status bits: None affected (as BLPD).

Words / Cycles: 1 word; 2 cycles (single execution, representative; as BLPD with a BMAR source).

Cycle class: see Instruction Timing.

Example: BLPD BMAR,00h - copy the BMAR-addressed program word into the dma.

BSAR

Barrel-shift the accumulator right by 1 to 16 bits in a single cycle.

Syntax: BSAR shift

Operation: (PC) + 1 -> PC; (ACC) / 2^shift -> ACC.

Operands: 1 <= shift <= 16.

Opcode:

15..8 = 1 0 1 1 1 1 1 1   bits7-4 = 1 1 1 0   bits3-0 = SHFT (see Table 6-1)
base: 0xBFE0   FMT 0x15

Status bits: Affected by SXM (SXM = 0 zero-fills the high bits; SXM = 1 sign-extends).

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: BSAR 4 - arithmetic right-shift the ACC by 4 bits.

BV

Branch if overflow: the OV bit is set (and OV is then cleared by the test, per the overflow-flag semantics). Not individually documented in the source range; a single-condition form of BCND (OV condition).

Syntax: BV pma (equivalent to BCND pma,OV; see BCND).

Operation: if (OV = 1): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE322  (1110 0011 0010 0010)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BV PGM191 - branch when OV = 1.

BZ

Branch if accumulator zero (EQ). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BZ pma (equivalent to BCND pma,EQ; see BCND).

Operation: if (ACC = 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE388  (1110 0011 1000 1000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BZ PGM191 - branch when ACC = 0.

CALA

Computed call: push the return address and branch to the address in the accumulator low word.

Syntax: CALA

Operation: (PC) + 1 -> TOS; (ACC(15-0)) -> PC.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 1 1 0 0 0 0
base: 0xBE30   FMT 0x00

Status bits: None affected.

Words / Cycles: 1 word; 4 cycles (single execution). Not repeatable.

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CALA instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
4	4	4	4+3p [a]

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: CALA - push PC+1, then continue at the ACC address.

CALAD

Delayed computed call; the following instruction word(s) execute before the call is taken.

Syntax: CALAD

Operation: (PC) + 3 -> TOS; (ACC(15-0)) -> PC (after the delay slot).

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 1 1 1 1 0 1
base: 0xBE3D   FMT 0x00

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single execution). Not repeatable.

Cycle class: XI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CALAD instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
2	2	2	2+p

Example: CALAD then MAR *+,AR1 / LDP #5 - delay-slot words execute, PC+3 is pushed, control passes to the ACC address.

CALL

Call a program-memory address: push the return address and branch, with an optional AR/ARP update.

Syntax: CALL pma [,{ind} [,ARn ] ]

Operation: (PC) + 2 -> TOS; pma -> PC; modify current AR and ARP as specified.

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 0 1 0   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7A80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles (single execution). Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CALL instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
4	4	4	4+4p [a]

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: CALL PRG191,*+,AR0 - push the return address, branch to PRG191, increment the current AR, set ARP = 0.

CALLD

Delayed call; the following instruction word(s) execute before the call is taken.

Syntax: CALLD pma [,{ind} [,ARn ] ]

Operation: (PC) + 4 -> TOS; pma -> PC; modify current AR and ARP as specified (after the delay slot).

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 1 1 0   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7E80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CALLD instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: CALLD PRG191 then MAR *+,AR1 / LDP #5 - delay-slot words execute, PC+4 is pushed, control passes to PRG191.

CC

Conditional call: if the condition(s) are met, push the return address and branch to pma; behaves like CALL when all conditions are true.

Syntax: CC pma, cond [,cond1 ] [,...]

Operation: if (condition(s)): (PC) + 2 -> TOS, pma -> PC; else (PC) + 2 -> PC.

Operands: 0 <= pma <= 65535; conditions as listed in "About the condition codes". NTC, TC, and BIO are mutually exclusive.

Opcode:

word 1:  15..10 = 1 1 1 0 1 0   bits9-8 = TP   bits7-4 = ZLVC   bits3-0 = ZLVC  (see Table 6-1)
word 2:  16-bit pma constant
base: 0xEB00   FMT 0x18

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles if the call is taken, 2 if not. Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CC instruction is not repeatable.

Cycles for a Single Instruction:

Condition	ROM	DARAM	SARAM	External Memory
True	4	4	4	4+4p [a]
False	2	2	2	2+2p

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: CC PGM191,LEQ,C - call PGM191 if ACC <= 0 and C = 1.

CCD

Delayed conditional call; the following instruction word(s) execute before the call is taken. Behaves like CALLD when all conditions are true.

Syntax: CCD pma, cond [,cond1 ] [,...]

Operation: if (condition(s)): (PC) + 4 -> TOS, pma -> PC; else (PC) + 2 -> PC (after the delay slot).

Operands: 0 <= pma <= 65535; conditions as listed in "About the condition codes". NTC, TC, and BIO are mutually exclusive.

Opcode:

word 1:  15..10 = 1 1 1 1 1 0   bits9-8 = TP   bits7-4 = ZLVC   bits3-0 = ZLVC  (see Table 6-1)
word 2:  16-bit pma constant
base: 0xFB00   FMT 0x18

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CCD instruction is not repeatable.

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: CCD PGM191,LEQ,C then MAR *+,AR1 / LDP #5 - delay-slot words execute, then the conditional call is taken.

CLRC

Clear a single CPU control/status bit.

Syntax: CLRC control bit

Operation: (PC) + 1 -> PC; 0 -> control bit.

Operands: control bit: {C, CNF, HM, INTM, OVM, SXM, TC, XF}.

Opcode:

Common field 15..6 = 1 0 1 1 1 1 1 0 0 1, bit5 = 0; bits4-0 select the control bit:
  INTM -> 0xBE40   OVM -> 0xBE42   CNF -> 0xBE44   SXM -> 0xBE46
  HM   -> 0xBE48   TC  -> 0xBE4A   XF  -> 0xBE4C   C   -> 0xBE4E
toolchain base: 0x0000   FMT 0x22

Opcode disagreement: the toolchain base 0x0000 (FMT 0x22) is a pseudo-base; it matches no encoding in the manual graphic. The real per-bit encodings form the 0xBE40..0xBE4E family shown above (derived from the CLRC opcode graphics in the source range). Note that CLRC CNF (0xBE44) coincides with the CNFD instruction.

Status bits: Affects the selected control bit.

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: CLRC TC - clear the TC bit (bit 11 of ST1).

CMPL

Complement the accumulator (ones complement).

Syntax: CMPL

Operation: (PC) + 1 -> PC; (ACC inverted) -> ACC.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 0 0 0 0 0 1
base: 0xBE01   FMT 0x00

Status bits: Does not affect C.

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: CMPL - replace the ACC with its logical inversion.

CMPR

Compare the current auxiliary register against the auxiliary register compare register (ARCR) and set TC to the result.

Syntax: CMPR CM

Operation: (PC) + 1 -> PC; compare (current AR) to (ARCR); set TC = 1 if the CM-selected relation holds, else 0.

Operands: 0 <= CM <= 3. CM = 00: AR = ARCR; 01: AR < ARCR; 10: AR > ARCR; 11: AR != ARCR. ARs are compared as unsigned integers.

Opcode:

15..8 = 1 0 1 1 1 1 1 1   bits7-2 = 0 1 0 0 0 1   bits1-0 = CM (see Table 6-1)
base: 0xBF44   FMT 0x0c

Status bits: Affected by NDX; not affected by SXM; affects TC; does not affect SXM.

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: CMPR 2 - set TC if the current AR > ARCR.

CNFD

Configure the on-chip RAM block as data memory (clear the CNF bit). Not given a separate entry in the provided source range. Its opcode 0xBE44 is identical to the CLRC CNF encoding derived from the in-range CLRC graphics, which corroborates the toolchain value.

Syntax: CNFD (no operands; equivalent to CLRC CNF).

Operation: not detailed in the source range (clears the CNF configuration bit; see CLRC).

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 1 0 0 0 1 0 0
base: 0xBE44   FMT 0x00

Status bits: Affects the CNF control bit (as CLRC CNF); otherwise not specified in the source range.

Words / Cycles: 1 word; cycle count not specified in the source range (CLRC-class control instruction: 1 cycle single execution).

Cycle class: see Instruction Timing.

Example: CNFD - configure the reconfigurable RAM block as data memory.

CNFP

Configure the on-chip RAM block as program memory (set the CNF bit). Not given a separate entry in the provided source range. Its opcode 0xBE45 is the companion (CNF-set) encoding one above CNFD (0xBE44 = CLRC CNF); the set form (SETC CNF) is outside the B-C range.

Syntax: CNFP (no operands; companion of SETC CNF).

Operation: not detailed in the source range (sets the CNF configuration bit).

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 1 0 0 0 1 0 1
base: 0xBE45   FMT 0x00

Status bits: Affects the CNF control bit; otherwise not specified in the source range.

Words / Cycles: 1 word; cycle count not specified in the source range.

Cycle class: see Instruction Timing.

Example: CNFP - configure the reconfigurable RAM block as program memory.

CONF

Configure on-chip RAM block(s) via a 2-bit operand. Not documented in the provided source range.

Syntax: not specified in the source range (takes a block-configuration operand).

Operation: not specified in the source range.

Operands: not specified in the source range.

Opcode:

toolchain base: 0x0000   FMT 0x0c

Opcode disagreement / unverifiable: the toolchain base 0x0000 (FMT 0x0c) is a pseudo-base and matches no encoding available in the provided source range, which does not contain a CONF entry. The true encoding could not be verified here.

Status bits: not specified in the source range.

Words / Cycles: not specified in the source range.

Cycle class: see Instruction Timing.

Example: not specified in the source range.

CPL

Compare a data-memory word against a long immediate constant or against the dynamic bit manipulation register (DBMR), and set TC to the result.

Syntax:

Direct: CPL [,#lk ] dma
Indirect: CPL [,#lk ] {ind} [,ARn ]

Operation: long immediate not specified: (PC)+1 -> PC, compare (DBMR) to (dma), TC = 1 if equal else 0. Long immediate specified: (PC)+2 -> PC, compare lk to (dma), TC = 1 if equal else 0.

Operands: 0 <= dma <= 127; lk: 16-bit constant; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

Long immediate NOT specified:  15..8 = 0 1 0 1 1 0 1 1   bit7 = 0 direct (dma) / 1 indirect  -> 0x5B00 / 0x5B80
Long immediate specified:      15..8 = 0 1 0 1 1 1 1 1   bit7 = 0 / 1   word2 = 16-bit lk    -> 0x5F00 / 0x5F80
toolchain base: 0x0006   FMT 0x1e

Opcode disagreement: the toolchain base 0x0006 (FMT 0x1e) is a pseudo-base; it matches no encoding in the manual graphic. The real encodings above are carried by the FMT-0x1e expansion and by the toolchain's variant mnemonics CPLI (0x5B00, DBMR compare) and CPLK (0x5F00, long-immediate compare).

Status bits: Not affected by SXM; affects TC.

Words / Cycles: 1 word (long immediate not specified) or 2 words (specified); 1 cycle (no long immediate) or 2 cycles (long immediate), single execution with an on-chip operand.

Cycle class: IIA (CPL); VIIa (CPL #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	2	2	2	2+2p
SARAM	2	2	2, 3 [a]	2+2p
External	2+d	2+d	2+d	3+d+2p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (long immediate specified):

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n+1	n+1	n+1	n+1+2p
SARAM	n+1	n+1	n+1, n+2 [a]	n+1+2p
External	n+1	n+1	n+1	n+2+2p

[a] If the operand and the code are in the same SARAM block

Example: CPL #060h,60h - compare the constant 060h against Data(60h) and set TC.

CPLI

Compare a data-memory word against the DBMR (long immediate not specified), direct addressing. Not a separate entry in the source range; this is the direct, no-long-immediate variant of CPL (see CPL). Its base opcode 0x5B00 matches the CPL "long immediate not specified, direct" encoding.

Syntax: CPL dma (this variant; see CPL).

Operation: (PC)+1 -> PC; compare (DBMR) to (dma); TC = 1 if equal else 0.

Operands: 0 <= dma <= 127.

Opcode:

15..8 = 0 1 0 1 1 0 1 1   bit7 = 0 (direct)   bits6-0 = dma
base: 0x5B00   FMT 0x01

Status bits: Not affected by SXM; affects TC (as CPL).

Words / Cycles: 1 word; 1 cycle (single execution, on-chip operand).

Cycle class: see Instruction Timing.

Example: CPL 60h - compare Data(60h) against the DBMR and set TC.

CPLK

Compare a data-memory word against a 16-bit long immediate constant, direct addressing. Not a separate entry in the source range; this is the direct, long-immediate variant of CPL (see CPL). Its base opcode 0x5F00 matches the CPL "long immediate specified, direct" encoding.

Syntax: CPL #lk, dma (this variant; see CPL).

Operation: (PC)+2 -> PC; compare lk to (dma); TC = 1 if equal else 0.

Operands: 0 <= dma <= 127; lk: 16-bit constant.

Opcode:

15..8 = 0 1 0 1 1 1 1 1   bit7 = 0 (direct)   bits6-0 = dma
word 2: 16-bit lk constant
base: 0x5F00   FMT 0x14

Status bits: Not affected by SXM; affects TC (as CPL).

Words / Cycles: 2 words; 2 cycles (single execution, on-chip operand).

Cycle class: see Instruction Timing.

Example: CPL #060h,60h - compare 060h against Data(60h) and set TC.

CRGT

Load the signed maximum of the accumulator and the accumulator buffer into both, and set the carry accordingly.

Syntax: CRGT

Operation: (PC) + 1 -> PC; compare (ACC) to (ACCB). If ACC > ACCB: ACC -> ACCB, 1 -> C. If ACC < ACCB: ACCB -> ACC, 0 -> C. If ACC = ACCB: 1 -> C.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 0 1 1 0 1 1
base: 0xBE1B   FMT 0x00

Status bits: Affects C (set when ACC >= ACCB, else cleared).

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: CRGT - with ACC = 5h and ACCB = 4h, both become 5h and C is set.

CRLT

Load the signed minimum of the accumulator and the accumulator buffer into both, and set the carry accordingly.

Syntax: CRLT

Operation: (PC) + 1 -> PC; compare (ACC) to (ACCB). If ACC < ACCB: ACC -> ACCB, 1 -> C. If ACC > ACCB: ACCB -> ACC, 0 -> C. If ACC = ACCB: 0 -> C.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 0 1 1 1 0 0
base: 0xBE1C   FMT 0x00

Status bits: Affects C (set when ACC < ACCB, else cleared).

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution:

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: CRLT - with ACC = 4h and ACCB = 5h, both become 4h and C is set.

DINT

Description: Disable-interrupt mnemonic. Not documented within the provided source range (SPRU056D chapter 6, lines 12363-14217); listed here from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE41 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

DMOV

Description: Copies a data-memory word up to the next-higher address, implementing the single-sample delay used by digital filters.

Syntax: DMOV dma (direct); DMOV {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> dma + 1

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0111 0 ddddddd; Indirect 0111 0111 1 .... Base hex 0x7700 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by CNF and OVLY.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM). Works only in on-chip data RAM; on external memory or memory-mapped registers it reads but performs no move.

Cycle class: V - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 3*	1+p
External	2+2d	2+2d	2+2d	5+2d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	2n-2	2n-2	2n-2, 2n+1*	2n-2+p
External	4n-2+2nd	4n-2+2nd	4n-2+2nd	4n+1+2nd+p

If the operand and the code are in the same SARAM block

Example: DMOV DAT8 copies Data(308h) into Data(309h), leaving 308h unchanged.

EHWBS

Description: Emulation opcode (toolchain mnemonic EHWBS). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBEB1 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

EHWBT

Description: Emulation opcode (toolchain mnemonic EHWBT). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBEB3 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

EINT

Description: Enable-interrupt mnemonic. Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE40 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

EMPSD

Description: Emulation opcode (toolchain mnemonic EMPSD). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBEB0 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

EMRET

Description: Emulation opcode (toolchain mnemonic EMRET). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE92 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

ESTOP

Description: Emulation opcode (toolchain mnemonic ESTOP). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE90 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

ESTPD

Description: Emulation opcode (toolchain mnemonic ESTPD). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE91 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

ETRAP

Description: Emulation opcode (toolchain mnemonic ETRAP). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE93 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

EXAR

Description: Swaps the accumulator with the accumulator buffer in a single cycle.

Syntax: EXAR

Operation: (PC) + 1 -> PC; (ACCB) <-> (ACC)

Operands: none

Opcode: 1011 1110 0001 1101. Base hex 0xBE1D (sl_DL.txt), matches the manual row.

Status bits: none affected.

Words / Cycles: Words 1; Cycles 1 (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: EXAR with ACC = 043h and ACCB = 02h leaves ACC = 02h and ACCB = 043h.

FORT

Description: Toolchain mnemonic FORT. Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0x0000 (sl_DL.txt, format code 0x0D). The 0x0000 value looks like a format seed rather than a literal opcode and cannot be verified against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

IDLE

Description: Halts the processor in power-down mode until an unmasked interrupt or reset occurs.

Syntax: IDLE

Operation: (PC) + 1 -> PC

Operands: none

Opcode: 1011 1110 0010 0010. Base hex 0xBE22 (sl_DL.txt), matches the manual row.

Status bits: Affected by INTM. With INTM set, execution resumes after IDLE; with INTM cleared, control branches to the interrupt service routine.

Words / Cycles: Words 1; Cycles 1 (single). Not repeatable. Timer and serial-port peripherals stay active during idle.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The IDLE instruction is not repeatable.

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Example: IDLE parks the processor until a reset or unmasked interrupt arrives.

IDLE1

Description: Alternate mnemonic for IDLE; the toolchain table assigns it the same encoding as IDLE.

Syntax: IDLE1

Operation: Same as IDLE (shared opcode): (PC) + 1 -> PC

Operands: none

Opcode: 1011 1110 0010 0010. Base hex 0xBE22 (sl_DL.txt), identical to IDLE.

Status bits: Same as IDLE (shared opcode): affected by INTM.

Words / Cycles: Words 1; Cycles 1 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: IDLE1 behaves as IDLE, parking the processor until an unmasked interrupt or reset.

IDLE2

Description: Enters a deeper power-down than IDLE by removing the functional clock, waiting for an unmasked interrupt or reset.

Syntax: IDLE2

Operation: (PC) + 1 -> PC

Operands: none

Opcode: 1011 1110 0010 0011. Base hex 0xBE23 (sl_DL.txt), matches the manual row.

Status bits: Affected by INTM.

Words / Cycles: Words 1; Cycles 1 (single). Not repeatable. Timer and serial-port peripherals are inactive; exit needs a low level of at least five machine cycles on an external interrupt, RS, or NMI.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The IDLE2 instruction is not repeatable.

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Example: IDLE2 parks the processor in low-power mode until a reset or unmasked external interrupt.

IN

Description: Reads a 16-bit word from an I/O port into data memory.

Syntax: IN dma, PA (direct); IN {ind}, PA [,ARn] (indirect)

Operation: (PC) + 2 -> PC; port address -> address bus; data bus -> dma; port address + 1 -> port address (per repeat)

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= PA <= 65535; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 1010 1111 0 ddddddd then a 16-bit port constant word; Indirect 1010 1111 1 ... then the 16-bit port constant. Base hex 0xAF00 (sl_DL.txt), matches the manual direct row.

Status bits: none affected.

Words / Cycles: Words 2; Cycles 2 + iosrc (single, destination in DARAM). With RPT the port address auto-increments and the body runs in one cycle once the pipeline is primed.

Cycle class: XXVI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
Destination: DARAM	2+iosrc	2+iosrc	2+iosrc	3+iosrc +2pcode
Destination: SARAM	2+iosrc	2+iosrc	2+iosrc , 3+iosrc *	3+iosrc +2pcode
Destination: External	3+ddst +iosrc	3+ddst +iosrc	3+ddst +iosrc	6+ddst +iosrc +2pcode

If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
Destination: DARAM	2n+niosrc	2n+niosrc	2n+niosrc	2n+1+niosrc +2pcode
Destination: SARAM	2n+niosrc	2n+niosrc	2n+niosrc , 2n+2+niosrc *	2n+1+niosrc +2pcode
Destination: External	4n-1+nddst +niosrc	4n-1+nddst +niosrc	4n-1+nddst +niosrc	4n+2+nddst +niosrc +2pcode

If the destination operand and the code are in the same SARAM block

Example: IN DAT7,PA5 reads I/O port 55h into data memory location 307h (DP = 6).

INTR

Description: Software interrupt that vectors to a selected interrupt location, pushing the return address.

Syntax: INTR K

Operation: (PC) + 1 -> stack; corresponding interrupt vector -> PC

Operands: 0 <= K <= 31

Opcode: 1011 1110 0 11 kkkkk (K in the INTR# field). Base hex 0xBE60 (sl_DL.txt), matches the manual row.

Status bits: Not affected by INTM; affects INTM. The INTR vector does not clear the matching IFR bit.

Words / Cycles: Words 1; Cycles 4 (single). Not repeatable.

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The INTR instruction is not repeatable.

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
4	4	4	4+3p*

The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: INTR 3 passes control to program-memory location 6h and pushes PC + 1.

LAC

Description: Earlier mnemonic for LACC (load accumulator with left shift); the toolchain table gives LAC and LACC the same encoding.

Syntax: LAC dma [,shift] (direct); LAC {ind} [,shift [,ARn]] (indirect); LAC #lk [,shift] (long immediate)

Operation: Same as LACC (shared opcode): shifted (dma) or shifted lk -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= shift <= 16; -32768 <= lk <= 32767; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Same bit rows as LACC. Direct with shift 0001 ssss 0 ddddddd (base 0x1000). sl_DL.txt lists LAC as 0x0001, a toolchain format seed that does not equal the 0x1000 direct-with-shift base; see the LACC and LACI sections.

Status bits: Same as LACC (shared opcode): affected by SXM.

Words / Cycles: Words 1 (direct/indirect) or 2 (long immediate); Cycles 1 (single, direct/indirect, operand in DARAM).

Cycle class: see Instruction Timing.

Example: LAC DAT6,4 loads Data(dma) left-shifted by 4 into ACC.

LACB

Description: Loads the accumulator from the accumulator buffer.

Syntax: LACB

Operation: (PC) + 1 -> PC; (ACCB) -> ACC

Operands: none

Opcode: 1011 1110 0001 1111. Base hex 0xBE1F (sl_DL.txt), matches the manual row.

Status bits: none affected.

Words / Cycles: Words 1; Cycles 1 (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: LACB copies ACCB (5555 AAAAh) into ACC.

LACC

Description: Loads the accumulator with a data-memory word or 16-bit constant, left-shifted by a shift code.

Syntax: LACC dma [,shift] (direct); LACC {ind} [,shift [,ARn]] (indirect); LACC #lk [,shift] (long immediate)

Operation: Direct/indirect: (dma) x 2^shift -> ACC. Long immediate: lk x 2^shift -> ACC. Low bits zero-filled; high bits sign-extended if SXM set, else zero-filled.

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= shift <= 16 (default 0); -32768 <= lk <= 32767; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct with shift 0001 ssss 0 ddddddd (base 0x1000); Indirect with shift 0001 ssss 1 ...; Direct with shift of 16 0110 1010 0 ddddddd (0x6A00); Indirect with shift of 16 0110 1010 1 ...; Long immediate with shift 1011 1111 1000 ssss then 16-bit constant (0xBF80). sl_DL.txt lists LACC as 0x0001, a format seed; the real direct-with-shift base 0x1000 is carried in the toolchain table under LACI.

Status bits: Affected by SXM.

Words / Cycles: Words 1 (direct/indirect) or 2 (long immediate); Cycles 1 (single, direct/indirect, operand in DARAM); long immediate is not repeatable.

Cycle class: IIA (LACC); III (LACC #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the long immediate addressing modes, the LACC instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing)

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: LACC #F000h,1 with SXM = 1 loads FFFF E000h into ACC.

LACI

Description: Toolchain-internal name for the concrete direct/indirect-with-shift encoding of LACC.

Syntax: LACI dma [,shift] (direct); LACI {ind} [,shift [,ARn]] (indirect)

Operation: Same as LACC direct/indirect (shared encoding): (dma) x 2^shift -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= shift <= 16; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct with shift 0001 ssss 0 ddddddd; Indirect with shift 0001 ssss 1 .... Base hex 0x1000 (sl_DL.txt), matching the manual LACC direct-with-shift base.

Status bits: Same as LACC (shared encoding): affected by SXM.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: see Instruction Timing.

Example: LACI dma,shift loads Data(dma) left-shifted into ACC, as LACC does.

LACK

Description: Older mnemonic that loads the accumulator with a zero-extended 8-bit constant; the toolchain table gives it the short-immediate encoding of LACL.

Syntax: LACK #k

Operation: Same as LACL short immediate (shared opcode): 0 -> ACC(31-8); k -> ACC(7-0)

Operands: 0 <= k <= 255

Opcode: 1011 1001 kkkkkkkk (8-bit constant). Base hex 0xB900 (sl_DL.txt), matching the manual LACL short-immediate row.

Status bits: Same as LACL (shared opcode): not affected by SXM; operand is not sign-extended.

Words / Cycles: Words 1; Cycles 1 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LACK #10h loads 010h into the accumulator.

LACL

Description: Loads the low accumulator with a data-memory word or an 8-bit constant and zero-fills the high half; never sign-extends.

Syntax: LACL dma (direct); LACL {ind} [,ARn] (indirect); LACL #k (short immediate)

Operation: (PC) + 1 -> PC. Direct/indirect: 0 -> ACC(31-16), (dma) -> ACC(15-0). Short immediate: 0 -> ACC(31-8), k -> ACC(7-0).

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= k <= 255; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0110 1001 0 ddddddd (0x6900); Indirect 0110 1001 1 ...; Short immediate 1011 1001 kkkkkkkk (0xB900). sl_DL.txt lists LACL as 0x0000, a format seed that matches neither form; the direct base is 0x6900 and the short-immediate base 0xB900 is carried under LACK.

Status bits: Not affected by SXM. The operand is treated as an unsigned 16-bit value.

Words / Cycles: Words 1; Cycles 1 (single, direct/indirect, operand in DARAM); short immediate is not repeatable.

Cycle class: IIA (LACL); I (LACL #k) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short immediate addressing modes, the LACL instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Example: LACL DAT1 (DP = 6) loads Data(301h) into ACCL with ACCH zeroed.

LACT

Description: Loads the accumulator from data memory with a dynamic left shift taken from the four LSBs of TREG1.

Syntax: LACT dma (direct); LACT {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) x 2^TREG1(3-0) -> ACC; sign-extended only if SXM set

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0110 1011 0 ddddddd; Indirect 0110 1011 1 .... Base hex 0x6B00 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by SXM.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM). Useful for denormalizing a floating-point number whose exponent fits in four bits.

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example: LACT DAT1 (DP = 6, SXM = 0, TREG1 = 14h) loads Data(301h) shifted by 4 into ACC.

LALK

Description: Older mnemonic for the long-immediate, shifted form of LACC.

Syntax: LALK #lk [,shift]

Operation: Same as LACC long immediate (shared opcode): lk x 2^shift -> ACC

Operands: -32768 <= lk <= 32767; 0 <= shift <= 16

Opcode: 1011 1111 1000 ssss then a 16-bit constant word. Base hex 0xBF80 (sl_DL.txt), matching the manual LACC long-immediate-with-shift row.

Status bits: Same as LACC (shared opcode): affected by SXM.

Words / Cycles: Words 2; Cycles 2 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LALK #0F000h,1 loads the shifted constant into ACC, as LACC #lk,shift does.

LAMM

Description: Loads the low accumulator from a memory-mapped register on page 0 without touching the DP; high half is zeroed.

Syntax: LAMM dma (direct); LAMM {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> ACC(15-0); 0 -> ACC(31-16). The nine MSBs of the address are forced to 0.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1000 0 ddddddd; Indirect 0000 1000 1 .... Base hex 0x0800 (sl_DL.txt), matches the manual direct row.

Status bits: Not affected by SXM.

Words / Cycles: Words 1; Cycles 1 (single, MMR operand).

Cycle class: IIB - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
MMR*	1	1	1	1+p
MMPORT	1+iosrc	1+iosrc	1+iodsrc	1+2+p+iodsrc

Add one more cycle for peripheral memory-mapped access

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
MMR**	n	n	n	n+p
MMPORT	n+miosrc	n+miosrc	n+miosrc	n+p+miosrc

** Add n more cycles for peripheral memory-mapped access

Example: LAMM BMAR loads the BMAR contents into ACC without modifying the DP.

LAR

Description: Loads an auxiliary register from data memory or from an 8-bit or 16-bit constant.

Syntax: LAR ARx, dma (direct); LAR ARx, {ind} [,ARn] (indirect); LAR ARx, #k (short immediate); LAR ARx, #lk (long immediate)

Operation: (PC) + 1 -> PC (2 for long immediate); (dma), k, or lk -> AR. The constant is treated as unsigned regardless of SXM.

Operands: 0 <= x <= 7; 0 <= dma <= 127; 0 <= n <= 7; 0 <= k <= 255; 0 <= lk <= 65535; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 0 AAA 0 ddddddd (AAA = ARX; base 0x0000); Indirect 0000 0 AAA 1 ...; Short immediate 1011 0 AAA kkkkkkkk (base 0xB000); Long immediate 1011 1111 0000 1 AAA then 16-bit constant (base 0xBF08). Base hex 0x0000 (sl_DL.txt) matches the direct base.

Status bits: Affected by NDX; not affected by SXM.

Words / Cycles: Words 1 (direct/indirect/short immediate) or 2 (long immediate); Cycles 2 (single, direct/indirect, source in DARAM); immediate forms are not repeatable.

Cycle class: XXVII (LAR); XXVIII (LAR ARn, #k); III (LAR ARn, #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short and long immediate addressing modes, the LAR instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM	2	2	2	2+pcode
Source: SARAM	2	2	2, 3*	2+pcode
Source: External	2+dsrc	2+dsrc	2+dsrc	3+dsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM	2n	2n	2n	2n+pcode
Source: SARAM	2n	2n	2n, 2n+1*	2n+pcode
Source: External	2n+ndsrc	2n+ndsrc	2n+ndsrc	2n+1+ndsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

Operand	ROM	DARAM	SARAM	External Memory
	2	2	2	2+pcode

If the source operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing)

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: LAR AR0,DAT16 (DP = 6) loads Data(310h) into AR0. In indirect mode a modification of the AR named by the instruction is ignored when it equals the ARP target.

LARK

Description: Older mnemonic for the short-immediate form of LAR (load auxiliary register with an 8-bit constant).

Syntax: LARK ARx, #k

Operation: Same as LAR short immediate (shared opcode): k -> AR

Operands: 0 <= x <= 7; 0 <= k <= 255

Opcode: 1011 0 AAA kkkkkkkk (AAA = ARX). Base hex 0xB000 (sl_DL.txt), matching the manual LAR short-immediate row.

Status bits: Same as LAR (shared opcode): affected by NDX; not affected by SXM.

Words / Cycles: Words 1; Cycles 2 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LARK AR4,#01h loads 01h into AR4.

LARP

Description: Load-auxiliary-register-pointer mnemonic. Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0x8B88 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

LDP

Description: Loads the nine data-memory page-pointer bits from a data-memory word or a 9-bit constant.

Syntax: LDP dma (direct); LDP {ind} [,ARn] (indirect); LDP #k (short immediate)

Operation: (PC) + 1 -> PC. Direct/indirect: nine LSBs of (dma) -> DP. Short immediate: k -> DP.

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= k <= 511; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1101 0 ddddddd (0x0D00); Indirect 0000 1101 1 ...; Short immediate 1011 110 kkkkkkkkk (9-bit constant, 0xBC00). sl_DL.txt lists LDP as 0x0001, a format seed; the direct base 0x0D00 is carried under LDPI and the short-immediate base 0xBC00 under LDPK.

Status bits: Affects DP.

Words / Cycles: Words 1; Cycles 2 (single, direct/indirect, source in DARAM); short immediate is not repeatable.

Cycle class: XXVII (LDP); XXVIII (LDP #k) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short immediate addressing modes, the LDP instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM	2	2	2	2+pcode
Source: SARAM	2	2	2, 3*	2+pcode
Source: External	2+dsrc	2+dsrc	2+dsrc	3+dsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM	2n	2n	2n	2n+pcode
Source: SARAM	2n	2n	2n, 2n+1*	2n+pcode
Source: External	2n+ndsrc	2n+ndsrc	2n+ndsrc	2n+1+ndsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

Operand	ROM	DARAM	SARAM	External Memory
	2	2	2	2+pcode

If the source operand and the code are in the same SARAM block

Example: LDP #0h clears the DP to page 0.

LDPI

Description: Toolchain-internal name for the concrete direct encoding of LDP.

Syntax: LDPI dma (direct); LDPI {ind} [,ARn] (indirect)

Operation: Same as LDP direct/indirect (shared encoding): nine LSBs of (dma) -> DP

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1101 0 ddddddd; Indirect 0000 1101 1 .... Base hex 0x0D00 (sl_DL.txt), matching the manual LDP direct base.

Status bits: Same as LDP (shared encoding): affects DP.

Words / Cycles: Words 1; Cycles 2 (single, source in DARAM).

Cycle class: see Instruction Timing.

Example: LDPI dma loads the page pointer from the nine LSBs of Data(dma), as LDP does.

LDPK

Description: Older mnemonic for the short-immediate form of LDP (load the page pointer from a 9-bit constant).

Syntax: LDPK #k

Operation: Same as LDP short immediate (shared opcode): k -> DP

Operands: 0 <= k <= 511

Opcode: 1011 110 kkkkkkkkk (9-bit constant). Base hex 0xBC00 (sl_DL.txt), matching the manual LDP short-immediate row.

Status bits: Same as LDP (shared opcode): affects DP.

Words / Cycles: Words 1; Cycles 2 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LDPK #0h sets the DP to page 0.

LMMR

Description: Loads a memory-mapped register on page 0 from any data-memory address given as a 16-bit source, leaving the DP unchanged.

Syntax: LMMR dma, #addr (direct); LMMR {ind}, #addr [,ARn] (indirect)

Operation: PFC -> MCS; (PC) + 2 -> PC; lk -> PFC; (src at PFC) -> (dst at lower 7 bits of dma) per repeat; PFC + 1 -> PFC; MCS -> PFC

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= addr <= 65535; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 1000 1001 0 ddddddd then a 16-bit address word; Indirect 1000 1001 1 ... then the 16-bit address. Base hex 0x8900 (sl_DL.txt), matches the manual direct row.

Status bits: none affected.

Words / Cycles: Words 2; Cycles 2 (single, source in DARAM, destination MMR). With RPT the source address auto-increments.

Cycle class: XXIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM / Destination: MMR**	2	2	2	2+2pcode
Source: SARAM / Destination: MMR**	2	2	2, 3*	2+2pcode
Source: External / Destination: MMR**	2+psrc	2+psrc	2+psrc	3+psrc +2pcode
Source: DARAM / Destination: MMPORT	3+iodst	3+iodst	3+iodst	5+2pcode +iodst
Source: SARAM / Destination: MMPORT	3+iodst	3+iodst	3+iodst , 4*	5+2pcode +iodst
Source: External / Destination: MMPORT	3+psrc +iodst	3+psrc +iodst	3+psrc +iodst	6+psrc +2pcode +iodst

If the source operand and the code are in the same SARAM block ** Add one more cycle for peripheral memory-mapped register access

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM / Destination: MMR***	2n	2n	2n	2n+2pcode
Source: SARAM / Destination: MMR***	2n	2n	2n, 2n+1*	2n+2pcode
Source: External / Destination: MMR***	2n+ndsrc	2n+ndsrc	2n+ndsrc	2n+1+ndsrc +2pcode
Source: DARAM / Destination: MMPORT	3n+niodst	3n+niodst	3n+niodst	3n+3+niodst +2pcode
Source: SARAM / Destination: MMPORT	3n+niodst	3n+niodst	3n+niodst , 3n+1+niodst *	3n+3+niodst +2pcode
Source: External / Destination: MMPORT	4n-1+ndsrc +niodst	4n-1+ndsrc +niodst	4n-1+ndsrc +niodst	4n+2+ndsrc + niodst +2pcode

If the source operand and the code are in the same SARAM block *** Add n more cycles for peripheral memory-mapped register access

Example: LMMR DBMR,#300h loads DBMR from Data(300h).

LPH

Description: Loads the high half of the product register from data memory, leaving the low half unchanged.

Syntax: LPH dma (direct); LPH {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> PREG(31-16)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0101 0 ddddddd; Indirect 0111 0101 1 .... Base hex 0x7500 (sl_DL.txt), matches the manual direct row.

Status bits: none affected.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM). Useful for restoring PREG high after interrupts or calls when automatic context save is not used.

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example: LPH DAT0 (DP = 4) sets PREG high to F79Ch, keeping PREG low.

LRLK

Description: Older mnemonic for the long-immediate form of LAR (load an auxiliary register with a 16-bit constant).

Syntax: LRLK ARx, #lk

Operation: Same as LAR long immediate (shared opcode): lk -> AR

Operands: 0 <= x <= 7; 0 <= lk <= 65535

Opcode: 1011 1111 0000 1 AAA then a 16-bit constant word (AAA = ARX). Base hex 0xBF08 (sl_DL.txt), matching the manual LAR long-immediate row.

Status bits: Same as LAR (shared opcode): affected by NDX; not affected by SXM.

Words / Cycles: Words 2; Cycles 2 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LRLK AR4,#3FFFh loads 3FFFh into AR4.

LST

Description: Restores a status register (ST0 or ST1) from data memory; the selector m chooses which register.

Syntax: LST #m, dma (direct); LST #m, {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> STm; dma(13-15) -> ARP regardless of n

Operands: 0 <= dma <= 127; m = 0 or 1; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: LST #0 direct 0000 1110 0 ddddddd (0x0E00); LST #0 indirect 0000 1110 1 ...; LST #1 direct 0000 1111 0 ddddddd (0x0F00); LST #1 indirect 0000 1111 1 .... sl_DL.txt lists LST as 0x0000, a format seed; the real form bases 0x0E00 and 0x0F00 are carried under LST0 and LST1.

Status bits: LST #0 affects ARB, ARP, C, CNF, DP, HM, OV, OVM, PM, SXM, TC, and XF but not INTM. For LST #1 the value loaded into ARB is also loaded into ARP.

Words / Cycles: Words 1; Cycles 2 (single, source in DARAM).

Cycle class: XXVII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM	2	2	2	2+pcode
Source: SARAM	2	2	2, 3*	2+pcode
Source: External	2+dsrc	2+dsrc	2+dsrc	3+dsrc +pcode

If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM	2n	2n	2n	2n+pcode
Source: SARAM	2n	2n	2n, 2n+1*	2n+pcode
Source: External	2n+ndsrc	2n+ndsrc	2n+ndsrc	2n+1+ndsrc +pcode

If the source operand and the code are in the same SARAM block

Example: LST #0,60h (DP = 0) loads ST0 from Data(60h), leaving INTM and ARB unchanged.

LST0

Description: Toolchain mnemonic for the LST #0 form (restore ST0 from data memory).

Syntax: LST0 dma (direct); LST0 {ind} [,ARn] (indirect)

Operation: Same as LST #0 (shared opcode): (dma) -> ST0; dma(13-15) -> ARP

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1110 0 ddddddd; Indirect 0000 1110 1 .... Base hex 0x0E00 (sl_DL.txt), matching the manual LST #0 direct row.

Status bits: Same as LST #0 (shared opcode): affects ARB, ARP, C, CNF, DP, HM, OV, OVM, PM, SXM, TC, and XF but not INTM.

Words / Cycles: Words 1; Cycles 2 (single, source in DARAM).

Cycle class: see Instruction Timing.

Example: LST0 60h loads ST0 from Data(60h), as LST #0 does.

LST1

Description: Toolchain mnemonic for the LST #1 form (restore ST1 from data memory).

Syntax: LST1 dma (direct); LST1 {ind} [,ARn] (indirect)

Operation: Same as LST #1 (shared opcode): (dma) -> ST1; value loaded into ARB is also loaded into ARP

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1111 0 ddddddd; Indirect 0000 1111 1 .... Base hex 0x0F00 (sl_DL.txt), matching the manual LST #1 direct row.

Status bits: Same as LST #1 (shared opcode): the value loaded into ARB is also loaded into ARP.

Words / Cycles: Words 1; Cycles 2 (single, source in DARAM).

Cycle class: see Instruction Timing.

Example: LST1 00h (DP = 6) loads ST1 from Data(300h), as LST #1 does.

LT

Description: Loads TREG0 from data memory in preparation for a multiply.

Syntax: LT dma (direct); LT {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; if TRM = 0 also (dma) -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0011 0 ddddddd; Indirect 0111 0011 1 .... Base hex 0x7300 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by TRM.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example: LT DAT24 (DP = 8, TRM = 1) loads Data(418h) into TREG0.

LTA

Description: Loads TREG0 from data memory and adds the shifted product register to the accumulator.

Syntax: LTA dma (direct); LTA {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; (ACC) + (shifted PREG) -> ACC; if TRM = 0 also -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0000 0 ddddddd; Indirect 0111 0000 1 .... Base hex 0x7000 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by OVM, PM, and TRM; affects C and OV.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example: LTA DAT36 (DP = 6, PM = 0, TRM = 1) loads Data(324h) into TREG0 and adds the shifted PREG to ACC.

LTD

Description: Like LTA but also moves the data word up one address (the DMOV delay), for on-chip RAM.

Syntax: LTD dma (direct); LTD {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; (dma) -> dma + 1; (ACC) + (shifted PREG) -> ACC; if TRM = 0 also -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0010 0 ddddddd; Indirect 0111 0010 1 .... Base hex 0x7200 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by OVM, PM, and TRM; affects C and OV.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM). On external data memory the data move does not occur and the operation matches LTA.

Cycle class: V - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 3*	1+p
External	2+2d	2+2d	2+2d	5+2d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	2n-2	2n-2	2n-2, 2n+1*	2n-2+p
External	4n-2+2nd	4n-2+2nd	4n-2+2nd	4n+1+2nd+p

If the operand and the code are in the same SARAM block

Example: LTD DAT126 (DP = 7, PM = 0, TRM = 1) loads TREG0, copies Data(3FEh) to 3FFh, and accumulates the shifted PREG.

LTP

Description: Loads TREG0 from data memory and stores the shifted product register into the accumulator (no add).

Syntax: LTP dma (direct); LTP {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; (shifted PREG) -> ACC; if TRM = 0 also -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0001 0 ddddddd; Indirect 0111 0001 1 .... Base hex 0x7100 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by PM and TRM.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example: LTP DAT36 (DP = 6, PM = 0, TRM = 1) loads TREG0 and stores the shifted PREG into ACC.

LTS

Description: Loads TREG0 from data memory and subtracts the shifted product register from the accumulator.

Syntax: LTS dma (direct); LTS {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; (ACC) - (shifted PREG) -> ACC; if TRM = 0 also -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0100 0 ddddddd; Indirect 0111 0100 1 .... Base hex 0x7400 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by OVM, PM, and TRM; affects C and OV. The C bit clears on a borrow, otherwise it sets.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

If the operand and the code are in the same SARAM block

Example: LTS DAT36 (DP = 6, PM = 0, TRM = 1) loads TREG0 and subtracts the shifted PREG from ACC.

MAC

Description: Multiply a data-memory value by a program-memory value and accumulate the shifted product into the ACC.

Syntax:

Direct: MAC pma, dma
Indirect: MAC pma, {ind} [,ARn]

Operation:

(ACC) + (shifted PREG) -> ACC
(dma) -> TREG0
(dma) x (pma, addressed by PFC) -> PREG
modify current AR and ARP as specified

Operands: 0 <= pma <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0xA200 (sl_M.txt).

Direct:    1 0 1 0 0 0 1 0 | 0 |      dma (7)        + 16-bit constant word
Indirect:  1 0 1 0 0 0 1 0 | 1 | indirect fields     + 16-bit constant word

Status bits: Affected by OVM, PM, and TRM. Affects C and OV.

Words / Cycles: 2 words; 3 cycles for a single instruction (both operands in DARAM/ROM).

Cycle class: XIX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 2

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
1: DARAM/ROM; 2: DARAM	3	3	3	3+2pcode
1: SARAM; 2: DARAM	3	3	3	3+2pcode
1: External; 2: DARAM	3+pop1	3+pop1	3+pop1	3+pop1 +2pcode
1: DARAM/ROM; 2: SARAM	3	3	3	3+2pcode
1: SARAM; 2: SARAM	3, 4[1]	3, 4[1]	3, 4[1]	3+2pcode , 4+2pcode [1]
1: External; 2: SARAM	3+pop1	3+pop1	3+pop1	3+pop1 +2pcode
1: DARAM/ROM; 2: External	3+dop2	3+dop2	3+dop2	3+dop2+2pcode
1: SARAM; 2: External	3+dop2	3+dop2	3+dop2	3+dop2 +2pcode
1: External; 2: External	4+pop1 +dop2	4+pop1 +dop2	4+pop1 +dop2	4+pop1 +dop2 +2pcode

[1] If both operands are in the same SARAM block.

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
1: DARAM/ROM; 2: DARAM	n+2	n+2	n+2	n+2+2pcode
1: SARAM; 2: DARAM	n+2	n+2	n+2	n+2+2pcode
1: External; 2: DARAM	n+2+npop1	n+2+npop1	n+2+npop1	n+2+npop1 +2pcode
1: DARAM/ROM; 2: SARAM	n+2	n+2	n+2	n+2+2pcode
1: SARAM; 2: SARAM	n+2, 2n+2[1]	n+2, 2n+2[1]	n+2, 2n+2[1]	n+2+2pcode , 2n+2[1]
1: External; 2: SARAM	n+2+npop1	n+2+npop1	n+2+npop1	n+2+npop1 +2pcode
1: DARAM/ROM; 2: External	n+2+ndop2	n+2+ndop2	n+2+ndop2	n+2+ndop2 +2pcode
1: SARAM; 2: External	n+2+ndop2	n+2+ndop2	n+2+ndop2	n+2+ndop2 +2pcode
1: External; 2: External	2n+2+npop1 +ndop2	2n+2+npop1 +ndop2	2n+2+npop1 +ndop2	2n+2+npop1 +ndop2 +2pcode

[1] If both operands are in the same SARAM block.

Example: MAC 0FF00h,02h ; accumulate (shifted PREG), then Data(302h) x Prog(FF00h) -> PREG.

MACD

Description: Same as MAC, with a data move of the on-chip RAM operand after the multiply.

Syntax:

Direct: MACD pma, dma
Indirect: MACD pma, {ind} [,ARn]

Operation:

(ACC) + (shifted PREG) -> ACC
(dma) -> TREG0
(dma) x (pma, addressed by PFC) -> PREG
(dma) -> (dma)+1            ; data move, on-chip RAM only
modify current AR and ARP as specified

Operands: 0 <= pma <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0xA300 (sl_M.txt).

Direct:    1 0 1 0 0 0 1 1 | 0 |      dma (7)        + 16-bit constant word
Indirect:  1 0 1 0 0 0 1 1 | 1 | indirect fields     + 16-bit constant word

Status bits: Affected by OVM, PM, and TRM. Affects C and OV.

Words / Cycles: 2 words; 3 cycles for a single instruction (both operands in DARAM/ROM). The data move occurs only within on-chip data RAM blocks; with external data memory the instruction acts as MAC.

Cycle class: XXI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 2

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
1: DARAM/ROM; 2: DARAM	3	3	3	3+2pcode
1: SARAM; 2: DARAM	3	3	3	3+2pcode
1: External; 2: DARAM	3+pop1	3+pop1	3+pop1	3+pop1 +2pcode
1: DARAM/ROM; 2: SARAM	3	3	3	3+2pcode
1: SARAM; 2: SARAM	3	3	3, 4[2], 5[3]	3+2pcode , 4+2pcode [2]
1: External; 2: SARAM	3+pop1	3+pop1	3+pop1	3+pop1 +2pcode
1: DARAM/ROM; 2: External[4]	3+dop2	3+dop2	3+dop2	3+dop2 +2pcode
1: SARAM; 2: External[4]	3+dop2	3+dop2	3+dop2	3+dop2 +2pcode
1: External; 2: External[4]	4+pop1 +dop2	4+pop1 +dop2	4+pop1 +dop2	4+pop1 +dop2 +2pcode

[2] If both operands are in the same SARAM block [3] If both operands and the code are in the same SARAM block [4] Data move operation is not performed when operand2 is in external data memory.

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
1: DARAM/ROM; 2: DARAM	n+2	n+2	n+2	n+2+2pcode
1: SARAM; 2: DARAM	n+2	n+2	n+2	n+2+2pcode
1: External; 2: DARAM	n+2+npop1	n+2+npop1	n+2+npop1	n+2+npop1 +2pcode
1: DARAM/ROM; 2: SARAM	2n	2n	2n, 2n+2[1]	2n+2pcode
1: SARAM; 2: SARAM	2n, 3n[2]	2n, 3n[2]	2n, 2n+2[1], 3n[2], 3n+2[3]	2n+2pcode , 3n[2]
1: External; 2: SARAM	2n+npop1	2n+npop1	2n+npop1 , 2n+2+npop1 [1]	2n+npop1 +2pcode
1: DARAM/ROM; 2: External[4]	n+2+ndop2	n+2+ndop2	n+2+ndop2	n+2+ndop2 +2pcode
1: SARAM; 2: External[4]	n+2+ndop2	n+2+ndop2	n+2+ndop2	n+2+ndop2 +2pcode
1: External; 2: External[4]	2n+2+npop1 +ndop2	2n+2+npop1 +ndop2	2n+2+npop1 +ndop2	2n+2+npop1 +ndop2 +2pcode

[1] If operand2 and code are in the same SARAM block [2] If both operands are in the same SARAM block [3] If both operands and the code are in the same SARAM block [4] Data move operation is not performed when operand2 is in external data memory.

Example: MACD 0FF00h,08h ; MAC plus Data(308h) copied to Data(309h).

MADD

Description: MAC from program memory with the pma taken from BMAR, plus a data move for on-chip RAM.

Syntax:

Direct: MADD dma
Indirect: MADD {ind} [,ARn]

Operation:

(BMAR) -> PFC
(ACC) + (shifted PREG) -> ACC
(dma) -> TREG0
(dma) x (pma, addressed by PFC) -> PREG
(dma) -> (dma)+1            ; data move, on-chip RAM only
modify current AR and ARP as specified

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0xAB00 (sl_M.txt).

Direct:    1 0 1 0 1 0 1 1 | 0 |      dma (7)
Indirect:  1 0 1 0 1 0 1 1 | 1 | indirect fields

Status bits: Affected by OVM and PM. Affects C and OV.

Words / Cycles: 1 word; 2 cycles for a single instruction (both operands in DARAM/ROM). Acts as MADS when the data operand is a memory-mapped register or external memory.

Cycle class: XXII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
1: DARAM/ROM; 2: DARAM	2	2	2	2+pcode
1: SARAM; 2: DARAM	2	2	2	2+pcode
1: External; 2: DARAM	2+pop1	2+pop1	2+pop1	2+pop1 +pcode
1: DARAM/ROM; 2: SARAM	2	2	2	2+pcode
1: SARAM; 2: SARAM	2	2	2, 3[2], 4[3]	2+pcode , 3+pcode [2]
1: External; 2: SARAM	2+pop1	2+pop1	2+pop1	2+pop1 +pcode
1: DARAM/ROM; 2: External[4]	2+dop2	2+dop2	2+dop2	2+dop2 +pcode
1: SARAM; 2: External[4]	2+dop2	2+dop2	2+dop2	2+dop2 +pcode
1: External; 2: External[4]	3+pop1 +dop2	3+pop1 +dop2	3+pop1 +dop2	3+pop1 +dop2 +pcode

[2] If both operands are in the same SARAM block [3] If both operands and code are in the same SARAM block [4] Data move operation is not performed when operand2 is in external data memory.

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
1: DARAM/ROM; 2: DARAM	n+1	n+1	n+1	n+1+pcode
1: SARAM; 2: DARAM	n+1	n+1	n+1	n+1+pcode
1: External; 2: DARAM	n+1+npop1	n+1+npop1	n+1+npop1	n+1+npop1 +pcode
1: DARAM/ROM; 2: SARAM	2n-1	2n-1	2n-1, 2n+1[1]	2n-1+pcode
1: SARAM; 2: SARAM	2n-1, 3n-1[2]	2n-1, 3n-1[2]	2n-1, 2n+1[1], 3n-1[2], 3n+1[3]	2n-1+pcode , 3n-1[2]
1: External; 2: SARAM	2n-1+npop1	2n-1+npop1	2n-1+npop1 , 2n+1+npop1 [1]	2n-1+npop1 +pcode
1: DARAM/ROM; 2: External[4]	n+1+ndop2	n+1+ndop2	n+1+ndop2	n+1+ndop2 +pcode
1: SARAM; 2: External[4]	n+1+ndop2	n+1+ndop2	n+1+ndop2	n+1+ndop2 +pcode
1: External; 2: External[4]	2n+1+npop1 +ndop2	2n+1+npop1 +ndop2	2n+1+npop1 +ndop2	2n+1+npop1 +ndop2 +pcode

[1] If operand2 and code are in the same SARAM block [2] If both operands are in the same SARAM block [3] If both operands and code are in the same SARAM block [4] Data move operation is not performed when operand2 is in external data memory.

Example: MADD DAT7 ; pma from BMAR, accumulate, then Data move within on-chip RAM.

MADS

Description: MAC from program memory with the pma taken from BMAR, without the data move.

Syntax:

Direct: MADS dma
Indirect: MADS {ind} [,ARn]

Operation:

(BMAR) -> PFC
(ACC) + (shifted PREG) -> ACC
(dma) -> TREG0
(dma) x (pma, addressed by PFC) -> PREG
modify current AR and ARP as specified

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0xAA00 (sl_M.txt).

Direct:    1 0 1 0 1 0 1 0 | 0 |      dma (7)
Indirect:  1 0 1 0 1 0 1 0 | 1 | indirect fields

Status bits: Affected by OVM and PM. Affects C and OV.

Words / Cycles: 1 word; 2 cycles for a single instruction (both operands in DARAM/ROM).

Cycle class: XX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
1: DARAM/ROM; 2: DARAM	2	2	2	2+pcode
1: SARAM; 2: DARAM	2	2	2	2+pcode
1: External; 2: DARAM	2+pop1	2+pop1	2+pop1	not specified in source
1: DARAM/ROM; 2: SARAM	2	2	2	2+pcode
1: SARAM; 2: SARAM	2, 3[1]	2, 3[1]	2, 3[1]	2+pcode , 3+pcode [1]
1: External; 2: SARAM	2+pop1	2+pop1	2+pop1	2+pop1+pcode
1: DARAM/ROM; 2: External	2+dop2	2+dop2	2+dop2	2+dop2 +pcode
1: SARAM; 2: External	2+dop2	2+dop2	2+dop2	2+dop2 +pcode
1: External; 2: External	3+pop1 +dop2	3+pop1 +dop2	3+pop1 +dop2	3+pop1 +dop2 +pcode

[1] If both operands are in the same SARAM block.

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
1: DARAM/ROM; 2: DARAM	n+1	n+1	n+1	n+1+pcode
1: SARAM; 2: DARAM	n+1	n+1	n+1	n+1+pcode
1: External; 2: DARAM	n+1+npop1	n+1+npop1	n+1+npop1	n+1+npop1 +pcode
1: DARAM/ROM; 2: SARAM	n+1	n+1	n+1	n+1+pcode
1: SARAM; 2: SARAM	n+1, 2n+1[1]	n+1, 2n+1[1]	n+1, 2n+1[1]	n+1+pcode , 2n+1[1]
1: External; 2: SARAM	n+1+npop1	n+1+npop1	n+1+npop1	n+1+npop1 +pcode
1: DARAM/ROM; 2: External	n+1+ndop2	n+1+ndop2	n+1+ndop2	n+1+ndop2 +pcode
1: SARAM; 2: External	n+1+ndop2	n+1+ndop2	n+1+ndop2	n+1+ndop2 +pcode
1: External; 2: External	2n+1+npop1 +ndop2	2n+1+npop1 +ndop2	2n+1+npop1 +ndop2	2n+1+npop1 +ndop2 +pcode

[1] If both operands are in the same SARAM block.

Example: MADS DAT12 ; pma from BMAR, Data(30Ch) x Prog(FF00h) -> PREG.

MAR

Description: Modify the auxiliary registers and ARP; the referenced memory is unaffected.

Syntax:

Direct: MAR dma
Indirect: MAR {ind} [,ARn]

Operation:

Indirect addressing: modify current AR and ARP as specified
Direct addressing:   executes as a NOP

Operands: 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0x8B00 (sl_M.txt).

Direct:    1 0 0 0 1 0 1 1 | 0 |      dma (7)
Indirect:  1 0 0 0 1 0 1 1 | 1 | indirect fields

Status bits: Affected by NDX.

Words / Cycles: 1 word; 1 cycle for a single instruction. LARP (from the 'C2x set) is a subset of MAR: MAR *,4 equals LARP 4.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: MAR *,AR1 ; load ARP with 1.

MPY

Description: Multiply TREG0 by a data-memory value or a constant and store the product in PREG.

Syntax:

Direct: MPY dma
Indirect: MPY {ind} [,ARn]
Short immediate: MPY #k
Long immediate: MPY #lk

Operation:

Direct/indirect:   (TREG0) x (dma) -> PREG
Short immediate:   (TREG0) x k     -> PREG     ; k sign-extended, regardless of SXM
Long immediate:    (TREG0) x lk    -> PREG

Operands: 0 <= dma <= 127; 0 <= n <= 7; -4096 <= k <= 4095; -32768 <= lk <= 32767; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0x0000 (sl_M.txt; see notes - this does not match any MPY field row in the manual). Manual field rows:

Direct:          0 1 0 1 0 1 0 0 | 0 |      dma (7)            base 0x5400
Indirect:        0 1 0 1 0 1 0 0 | 1 | indirect fields         base 0x5400
Short immediate: 1 1 0 |            13-bit constant            base 0xC000
Long immediate:  1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0              base 0xBE80
                 + 16-bit constant word

Status bits: Affected by TRM. Not affected by SXM.

Words / Cycles: 1 word (direct, indirect, or short immediate), 2 words (long immediate); 1 cycle for a single direct/indirect instruction (DARAM), 2 cycles for long immediate. Not repeatable in the short or long immediate modes.

Cycle class: IIA (MPY); I (MPY #k); III (MPY #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1 (Direct, indirect, or short immediate addressing); 2 (Long immediate addressing)

For the short and long immediate addressing modes, the MPY instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2[1]	1+p
External	1+d	1+d	1+d	2+d+p

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1[1]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[1] If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Single Instruction (long immediate addressing)

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: MPY DAT13 ; TREG0 x Data(40Dh) -> PREG.

MPYA

Description: Accumulate the shifted PREG into the ACC, then multiply TREG0 by a data-memory value into PREG.

Syntax:

Direct: MPYA dma
Indirect: MPYA {ind} [,ARn]

Operation:

(ACC) + (shifted PREG) -> ACC
(TREG0) x (dma) -> PREG

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0x5000 (sl_M.txt).

Direct:    0 1 0 1 0 0 0 0 | 0 |      dma (7)
Indirect:  0 1 0 1 0 0 0 0 | 1 | indirect fields

Status bits: Affected by OVM, PM, and TRM. Affects C and OV.

Words / Cycles: 1 word; 1 cycle for a single instruction (DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2[1]	1+p
External	1+d	1+d	1+d	2+d+p

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1[1]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[1] If the operand and the code are in the same SARAM block

Example: MPYA DAT13 ; add shifted PREG to ACC, then TREG0 x Data(30Dh) -> PREG.

MPYI

Description: Not specified (no dedicated entry in the provided source range). The toolchain opcode matches the MPY direct/indirect field row (base 0x5400).

Syntax: not specified in the provided source range.

Operation: not specified in the provided source range.

Operands: not specified in the provided source range.

Opcode: base hex 0x5400 (sl_M.txt). This equals the MPY direct/indirect opcode row in the manual:

0 1 0 1 0 1 0 0 | mode bit | dma or indirect fields     base 0x5400

Status bits: not specified in the provided source range.

Words / Cycles: not specified in the provided source range.

Cycle class: see Instruction Timing.

Example: not specified in the provided source range.

MPYK

Description: Multiply TREG0 by a signed 13-bit short-immediate constant into PREG (the short-immediate form documented under the MPY entry).

Syntax: MPY #k

Operation:

(TREG0) x k -> PREG        ; k is right-justified and sign-extended, regardless of SXM

Operands: -4096 <= k <= 4095

Opcode: base hex 0xC000 (sl_M.txt), matching the MPY short-immediate field row:

1 1 0 |              13-bit constant

Status bits: Affected by TRM. Not affected by SXM.

Words / Cycles: 1 word; 1 cycle for a single instruction. Not repeatable.

Cycle class: see Instruction Timing.

Example: MPY #031h ; TREG0 x 31h -> PREG.

MPYS

Description: Subtract the shifted PREG from the ACC, then multiply TREG0 by a data-memory value into PREG.

Syntax:

Direct: MPYS dma
Indirect: MPYS {ind} [,ARn]

Operation:

(ACC) - (shifted PREG) -> ACC
(TREG0) x (dma) -> PREG

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0x5100 (sl_M.txt).

Direct:    0 1 0 1 0 0 0 1 | 0 |      dma (7)
Indirect:  0 1 0 1 0 0 0 1 | 1 | indirect fields

Status bits: Affected by OVM, PM, and TRM. Affects C and OV. The C bit is cleared on a borrow; otherwise it is set.

Words / Cycles: 1 word; 1 cycle for a single instruction (DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2[1]	1+p
External	1+d	1+d	1+d	2+d+p

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1[1]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[1] If the operand and the code are in the same SARAM block

Example: MPYS DAT13 ; subtract shifted PREG from ACC, then TREG0 x Data(30Dh) -> PREG.

MPYU

Description: Unsigned multiply of TREG0 by a data-memory value into PREG.

Syntax:

Direct: MPYU dma
Indirect: MPYU {ind} [,ARn]

Operation:

unsigned (TREG0) x unsigned (dma) -> PREG

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0x5500 (sl_M.txt).

Direct:    0 1 0 1 0 1 0 1 | 0 |      dma (7)
Indirect:  0 1 0 1 0 1 0 1 | 1 | indirect fields

Status bits: Affected by TRM. Not affected by SXM. The multiplier acts as a signed 17 x 17-bit multiplier with the MSB of both operands forced to 0; the p-scaler always sign-extends PREG in right-shift-by-6 mode (PM = 11 binary), so that shift mode should not be used for unsigned products.

Words / Cycles: 1 word; 1 cycle for a single instruction (DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2[1]	1+p
External	1+d	1+d	1+d	2+d+p

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1[1]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[1] If the operand and the code are in the same SARAM block

Example: MPYU DAT16 ; unsigned FFFFh x FFFFh -> PREG = FFFE0001h.

MRKL

Description: Not specified (no dedicated entry in the provided source range).

Syntax: not specified in the provided source range.

Operation: not specified in the provided source range.

Operands: not specified in the provided source range.

Opcode: base hex 0xBE80 (sl_M.txt). This value equals the MPY long-immediate opcode in the manual (1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 = 0xBE80); see notes.

Status bits: not specified in the provided source range.

Words / Cycles: not specified in the provided source range.

Cycle class: see Instruction Timing.

Example: not specified in the provided source range.

Opcode cross-check notes

MAC (0xA200), MACD (0xA300), MADD (0xAB00), MADS (0xAA00), MAR (0x8B00), MPYA (0x5000), MPYS (0x5100), MPYU (0x5500): toolchain base hex agrees with the manual's direct-addressing opcode field row.
MPY: sl_M.txt lists base 0x0000, which matches no MPY field row in the manual. The manual's MPY forms are direct/indirect 0x5400, short immediate 0xC000, and long immediate 0xBE80. In the toolchain table those forms appear to be carried by separate rows: MPYI = 0x5400 and MPYK = 0xC000. The 0x0000 assigned to "MPY" is unexplained by the manual (likely a dispatch placeholder in c5x_isa.h).
MPYI (0x5400): no dedicated manual entry in the provided source range; opcode equals the MPY direct/indirect row.
MPYK (0xC000): no dedicated manual entry, but the value and semantics match the short-immediate form documented inside the MPY entry.
MRKL (0xBE80): no dedicated manual entry in the provided source range; the opcode collides with the MPY long-immediate opcode (0xBE80). This is a genuine disagreement that cannot be resolved from the provided range.

NEG

Negate (2s complement) the accumulator.

Syntax: NEG

Operation: (PC) + 1 -> PC; (ACC) x -1 -> ACC; if (ACC) != 0 then 0 -> C, if (ACC) = 0 then 1 -> C.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  0  0  0  0  1  0   = 0xBE02

Base opcode (toolchain table): 0xBE02.

Status bits: Affected by OVM. Affects C and OV. Negating 8000 0000h sets OV; with OVM set the result saturates to 7FFF FFFFh, with OVM cleared it stays 8000 0000h.

Words / Cycles: 1 word; 1 cycle (single, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: NEG ; ACC = -ACC

NMI

Force a nonmaskable interrupt to vector 24h.

Syntax: NMI

Operation: (PC) + 1 -> stack; 24h -> PC; 1 -> INTM.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  1  0  1  0  0  1  0   = 0xBE52

Base opcode (toolchain table): 0xBE52.

Status bits: Not affected by INTM. Affects INTM. No automatic context save is performed.

Words / Cycles: 1 word; 4 cycles (single; not repeatable).

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The NMI instruction is not repeatable.

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	4	4	4	4+3p*

* The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: NMI ; control passes to 24h, PC+1 pushed

NOP

No operation.

Syntax: NOP

Operation: (PC) + 1 -> PC.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  0  0  1  0  1  1   0  0  0  0  0  0  0  0   = 0x8B00

Base opcode (toolchain table): 0x8B00.

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: NOP

NORM

Normalize the signed accumulator by one bit, generating an exponent in the current AR.

Syntax: NORM {ind}

Operation: (PC) + 1 -> PC; if (ACC) = 0 then TC -> 1; else if ACC(31) XOR ACC(30) = 0 then TC -> 0, (ACC) x 2 -> ACC, modify current AR as specified; else TC -> 1.

Operands: ind: {* *+ *- *0+ *0- *BR0+ *BR0-}. The default AR modification is an increment.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  0  0  0  0  0   1  [ indirect fields: see Addressing Modes, Section 5.2 ]

Base opcode (toolchain table): 0xA080.

Status bits: Affects TC.

Words / Cycles: 1 word; 1 cycle (single). The AR used must not be touched by the next two instruction words.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: NORM *+

OPL

OR a data-memory word with a long immediate constant or with the DBMR, result back to memory (PLU instruction).

Syntax: OPL [#lk], dma (direct); OPL [#lk], {ind} [,ARn] (indirect). The two encoding forms are OPLI (no immediate) and OPLK (long immediate specified).

Operation: No immediate: (PC) + 1 -> PC, (dma) OR (DBMR) -> dma. Long immediate: (PC) + 2 -> PC, (dma) OR lk -> dma. ACC is unaffected.

Operands: 0 <= dma <= 127; lk: 16-bit constant; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}. Direct addressing with long immediate is not specified in the manual.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  1  0  1  1  0  0  1   0  [            dma           ]    direct, no immediate   (0x5900)
  0  1  0  1  1  0  0  1   1  [ indirect: see Section 5.2 ]   indirect, no immediate
  0  1  0  1  1  1  0  1   0  [            dma           ]    direct, long immediate (0x5D00)
  0  1  0  1  1  1  0  1   1  [ indirect: see Section 5.2 ]   indirect, long immediate

Base opcode (toolchain table): 0x0004 (toolchain PLU format-group base, FMT 0x1e; the real per-form encodings are 0x5900 for OPLI and 0x5D00 for OPLK).

Status bits: Affects TC. If the OR result is 0, TC is set; otherwise cleared.

Words / Cycles: 1 word (no immediate) or 2 words (long immediate); 1 cycle (no immediate, DARAM) or 2 cycles (long immediate).

Cycle class: V (OPL); VI (OPL) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the long immediate addressing modes, see the separate tables below.

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 3*	1+p
External	2+2d	2+2d	2+2d	5+2d+p

* If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	2n-2	2n-2	2n-2, 2n+1*	2n-2+p
External	4n-2+2nd	4n-2+2nd	4n-2+2nd	4n+1+2nd+p

* If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	2	2	2	2+2p
SARAM	2	2	2	2+2p
External	3+2d	3+2d	3+2d	6+2d+2p

Cycles for a Repeat (RPT) Execution (long immediate specified)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n+1	n+1	n+1	n+1+2p
SARAM	2n-1	2n-1	2n-1, 2n+2*	2n-1+2p
External	4n-1+2nd	4n-1+2nd	4n-1+2nd	4n+2+2nd+2p

* If the operand and the code are in the same SARAM block

Example: OPL #0FFFh,DAT10

OPLI

OPL encoding form: OR the data-memory word with the DBMR, result back to memory (no immediate).

Syntax: OPL dma (direct); OPL {ind} [,ARn] (indirect). This is the no-immediate form of OPL.

Operation: (PC) + 1 -> PC; (dma) OR (DBMR) -> dma.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  1  0  1  1  0  0  1   0  [            dma           ]    direct    (0x5900)
  0  1  0  1  1  0  0  1   1  [ indirect: see Section 5.2 ]   indirect

Base opcode (toolchain table): 0x5900.

Status bits: Affects TC (set if the OR result is 0, else cleared).

Words / Cycles: 1 word; 1 cycle (single, DARAM).

Cycle class: see Instruction Timing.

Example: OPL DAT10 ; OR data word with DBMR

OPLK

OPL encoding form: OR the data-memory word with a long immediate constant, result back to memory.

Syntax: OPL #lk, dma (direct); OPL #lk, {ind} [,ARn] (indirect). This is the long-immediate form of OPL.

Operation: (PC) + 2 -> PC; (dma) OR lk -> dma.

Operands: 0 <= dma <= 127; lk: 16-bit constant; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  1  0  1  1  1  0  1   0  [            dma           ]    direct    (0x5D00)
  0  1  0  1  1  1  0  1   1  [ indirect: see Section 5.2 ]   indirect
                              [ 16-bit constant in second word ]

Base opcode (toolchain table): 0x5D00.

Status bits: Affects TC (set if the OR result is 0, else cleared).

Words / Cycles: 2 words; 2 cycles (single, DARAM).

Cycle class: see Instruction Timing.

Example: OPL #0FFFh,DAT10

OR

OR a data-memory word or a shifted long immediate into the accumulator.

Syntax: OR dma (direct); OR {ind} [,ARn] (indirect); OR #lk [,shift] (long immediate). The encoding forms are ORI (direct/indirect) and ORK (long immediate with shift).

Operation: Direct/indirect: (PC) + 1 -> PC, (ACC(15-0)) OR (dma) -> ACC(15-0), ACC(31-16) unchanged. Long immediate: (PC) + 2 -> PC, (ACC) OR (lk << shift) -> ACC.

Operands: 0 <= dma <= 127; 0 <= n <= 7; lk: 16-bit constant; 0 <= shift <= 16; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  1  1  0  1  1  0  1   0  [            dma           ]    direct    (0x6D00)
  0  1  1  0  1  1  0  1   1  [ indirect: see Section 5.2 ]   indirect
  1  0  1  1  1  1  1  1   1  1  0  0  [   SHFT   ]            long immediate with shift (0xBFC0)
  1  0  1  1  1  1  1  0   1  0  0  0  0  0  1  0            long immediate, shift of 16 (0xBE82)
                              [ 16-bit constant in second word ]

Base opcode (toolchain table): 0x0001 (toolchain format-group base, FMT 0x1e; per-form encodings are 0x6D00 for ORI and 0xBFC0 for ORK). The SHFT field references Table 6-1 (page 6-2), which is outside the provided range.

Status bits: Does not affect C. Not affected by SXM (long immediate).

Words / Cycles: 1 word (direct/indirect) or 2 words (long immediate); 1 cycle (direct/indirect, DARAM) or 2 cycles (long immediate). Long immediate is not repeatable.

Cycle class: IIA (OR); III (OR #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the long immediate addressing modes, the OR instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

* If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

* If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing)

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	2	2	2	2+2p

Example: OR #08111h,8

ORB

OR the accumulator buffer (ACCB) into the accumulator.

Syntax: ORB

Operation: (PC) + 1 -> PC; (ACC) OR (ACCB) -> ACC.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  0  1  0  0  1  1   = 0xBE13

Base opcode (toolchain table): 0xBE13.

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: ORB

ORI

OR encoding form: OR a data-memory word into the accumulator low half (direct/indirect).

Syntax: OR dma (direct); OR {ind} [,ARn] (indirect). This is the direct/indirect form of OR.

Operation: (PC) + 1 -> PC; (ACC(15-0)) OR (dma) -> ACC(15-0); ACC(31-16) unchanged.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  1  1  0  1  1  0  1   0  [            dma           ]    direct    (0x6D00)
  0  1  1  0  1  1  0  1   1  [ indirect: see Section 5.2 ]   indirect

Base opcode (toolchain table): 0x6D00.

Status bits: Does not affect C.

Words / Cycles: 1 word; 1 cycle (single, DARAM).

Cycle class: see Instruction Timing.

Example: OR DAT8

ORK

OR encoding form: OR a shifted long immediate constant into the accumulator.

Syntax: OR #lk [,shift]. This is the long-immediate-with-shift form of OR.

Operation: (PC) + 2 -> PC; (ACC) OR (lk << shift) -> ACC. The constant is shifted per the shift code and zero-extended on both ends.

Operands: lk: 16-bit constant; 0 <= shift <= 16.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  1   1  1  0  0  [   SHFT   ]            shift 0..15 (0xBFC0)
  1  0  1  1  1  1  1  0   1  0  0  0  0  0  1  0            shift of 16  (0xBE82)
                              [ 16-bit constant in second word ]

Base opcode (toolchain table): 0xBFC0. The SHFT field references Table 6-1 (page 6-2), which is outside the provided range.

Status bits: Does not affect C. Not affected by SXM.

Words / Cycles: 2 words; 2 cycles (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: OR #08111h,8

OUT

Write a data-memory word to an I/O port.

Syntax: OUT dma, PA (direct); OUT {ind}, PA [,ARn] (indirect).

Operation: (PC) + 2 -> PC; port address -> A15-A0; (dma) -> D15-D0; under RPT the port address is incremented after each access. The IS line goes low to indicate an I/O access.

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= PA <= 65535; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  0  0  0  1  1  0  0   0  [            dma           ]    direct    (0x0C00)
  0  0  0  0  1  1  0  0   1  [ indirect: see Section 5.2 ]   indirect
                              [ 16-bit port constant in second word ]

Base opcode (toolchain table): 0x0C00.

Status bits: None affected.

Words / Cycles: 2 words; 3+iodst cycles (single, source DARAM).

Cycle class: XXV - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM	3+iodst	3+iodst	3+iodst	5+iodst+2pcode
Source: SARAM	3+iodst	3+iodst	3+iodst, 4+iodst*	5+iodst+2pcode
Source: External	3+dsrc+iodst	3+dsrc+iodst	3+dsrc+iodst	6+dsrc+iodst+2pcode

* If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM	3n+niodst	3n+niodst	3n+niodst	3n+3+niodst+2pcode
Source: SARAM	3n+niodst	3n+niodst	3n+niodst, 3n+1+niodst*	3n+3+niodst+2pcode
Source: External	5n-2+ndsrc+niodst	5n-2+ndsrc+niodst	5n-2+ndsrc+niodst	5n+1+ndsrc+niodst+2pcode

* If the source operand and the code are in the same SARAM block

Example: OUT *,PA15 ; write word at current AR to port 5Fh

PAC

Load the shifted product register into the accumulator.

Syntax: PAC

Operation: (PC) + 1 -> PC; (shifted PREG) -> ACC.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  0  0  0  0  1  1   = 0xBE03

Base opcode (toolchain table): 0xBE03.

Status bits: Affected by PM (the product shift mode defines the PREG shift).

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: PAC

POP

Pop the top of stack into the accumulator low half.

Syntax: POP

Operation: (PC) + 1 -> PC; (TOS) -> ACC(15-0); 0 -> ACC(31-16); pop stack one level.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  1  1  0  0  1  0   = 0xBE32

Base opcode (toolchain table): 0xBE32.

Status bits: None affected. The hardware stack is eight-deep LIFO; no underflow check exists.

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: POP

POPD

Pop the top of stack into a data-memory location.

Syntax: POPD dma (direct); POPD {ind} [,ARn] (indirect).

Operation: (PC) + 1 -> PC; (TOS) -> dma; pop stack one level (lower seven locations).

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  0  0  1  0  1  0   0  [            dma           ]    direct    (0x8A00)
  1  0  0  0  1  0  1  0   1  [ indirect: see Section 5.2 ]   indirect

Base opcode (toolchain table): 0x8A00.

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single, DARAM).

Cycle class: IVA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	2+d	2+d	2+d	4+d+p

* If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+2*	n+p
External	2n+nd	2n+nd	2n+nd	2n+2+nd+p

* If the operand and the code are in the same SARAM block

Example: POPD *+,AR1

PSHD

Push a data-memory word onto the stack.

Syntax: PSHD dma (direct); PSHD {ind} [,ARn] (indirect).

Operation: (dma) -> TOS; (PC) + 1 -> PC; push all stack locations down one level (lowest location is lost).

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  1  1  1  0  1  1  0   0  [            dma           ]    direct    (0x7600)
  0  1  1  1  0  1  1  0   1  [ indirect: see Section 5.2 ]   indirect

Base opcode (toolchain table): 0x7600.

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single, DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

* If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1*	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

* If the operand and the code are in the same SARAM block

Example: PSHD *,AR1

PUSH

Push the accumulator low half onto the stack.

Syntax: PUSH

Operation: (PC) + 1 -> PC; push all stack locations down one level; ACC(15-0) -> TOS.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  1  1  1  1  0  0   = 0xBE3C

Base opcode (toolchain table): 0xBE3C.

Status bits: None affected. More than eight pushes before a pop lose the oldest values.

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: PUSH

RC

Clear the carry bit (CLRC C alias).

Description: Not specified. The descriptive entry for RC is outside the provided SPRU056D range (RC is assembled as a CLRC-mode alias); only the toolchain opcode is available here.

Syntax: not specified.

Operation: not specified.

Operands: not specified.

Opcode: base opcode (toolchain table): 0xBE4E. Bit field row: not specified (outside the provided range).

Status bits: not specified.

Words / Cycles: not specified.

Cycle class: see Instruction Timing.

Example: not specified.

RET

Return from subroutine.

Syntax: RET

Operation: (TOS) -> PC; pop stack one level.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  1  1  0  1  1  1  1   0  0  0  0  0  0  0  0   = 0xEF00

Base opcode (toolchain table): 0xEF00.

Status bits: None affected.

Words / Cycles: 1 word; 4 cycles (single; not repeatable).

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RET instruction is not repeatable.

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	4	4	4	4+3p*

* The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: RET

RETC

Conditional return from subroutine.

Syntax: RETC cond [, cond1] [,...]

Operation: If the condition(s) are met: (TOS) -> PC, pop stack one level; else continue.

Operands: Conditions: EQ, NEQ, LT, LEQ, GT, GEQ, NC, C, NOV, OV, BIO, NTC, TC, UNC. Not all combinations are meaningful.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  1  1  0  1  1  [ TP ]  [   ZLVC   ]  [   ZLVC   ]   base 0xEF00

Base opcode (toolchain table): 0xEF00 (conditional format, FMT 0x1a). The TP and ZLVC condition fields reference Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected.

Words / Cycles: 1 word; 4 cycles if the condition is true, 2 cycles if false (not repeatable).

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RETC instruction is not repeatable.

Cycles for a Single Instruction

Condition	ROM	DARAM	SARAM	External Memory
True	4	4	4	4+3p*
False	2	2	2	2+p

* The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: RETC GEQ,NOV

RETCD

Delayed conditional return from subroutine.

Syntax: RETCD cond [, cond1] [,...]

Operation: The one 2-word (or two 1-word) instructions following RETCD are executed first; then, if the condition(s) are met, (TOS) -> PC and pop one level; else continue. The two following words do not affect the tested conditions.

Operands: Conditions: EQ, NEQ, LT, LEQ, GT, GEQ, NC, C, NOV, OV, BIO, NTC, TC, UNC.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  1  1  1  1  1  [ TP ]  [   ZLVC   ]  [   ZLVC   ]   base 0xFF00

Base opcode (toolchain table): 0xFF00 (conditional format, FMT 0x1a). The TP and ZLVC fields reference Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single; not repeatable).

Cycle class: XI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RETCD instruction is not repeatable.

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	2	2	2	2+p

Example: RETCD C

RETD

Delayed return from subroutine.

Syntax: RETD

Operation: The one 2-word (or two 1-word) instructions following RETD are executed first; then (TOS) -> PC and pop stack one level.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  1  1  1  1  1  1  1   0  0  0  0  0  0  0  0   = 0xFF00

Base opcode (toolchain table): 0xFF00.

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single; not repeatable).

Cycle class: XI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RETD instruction is not repeatable.

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	2	2	2	2+p

Example: RETD

RETE

Return from interrupt, enabling interrupts and restoring shadow registers.

Syntax: RETE

Operation: (TOS) -> PC; pop stack one level; 0 -> INTM. Equivalent to clearing INTM and executing RETI.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  1  1  1  0  1  0   = 0xBE3A

Base opcode (toolchain table): 0xBE3A.

Status bits: Affects ARB, ARP, AVIS, BRAF, C, CNF, DP, HM, INTM, MP/MC, NDX, OV, OVLY, OVM, PM, RAM, SXM, TC, TRM, and XF.

Words / Cycles: 1 word; 4 cycles (single; not repeatable).

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RETE instruction is not repeatable.

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	4	4	4	4+3p*

* The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: RETE

RETI

Return from interrupt, restoring shadow registers.

Syntax: RETI

Operation: (TOS) -> PC; pop stack one level. Shadow registers (ACC, ACCB, ARCR, INDX, PMST, PREG, ST0, ST1, TREG0, TREG1, TREG2) are returned to their strategic registers.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  1  1  1  0  0  0   = 0xBE38

Base opcode (toolchain table): 0xBE38.

Status bits: Affects ARB, ARP, AVIS, BRAF, C, CNF, DP, HM, MP/MC, NDX, OV, OVLY, OVM, PM, RAM, SXM, TC, TRM, and XF. Does not affect INTM.

Words / Cycles: 1 word; 4 cycles (single; not repeatable).

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RETI instruction is not repeatable.

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	4	4	4	4+3p*

* The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: RETI

RFSM

Reset frame-synchronization mode (CLRC-mode alias).

Description: Not specified. The descriptive entry for RFSM is outside the provided SPRU056D range; only the toolchain opcode is available here.

Syntax: not specified.

Operation: not specified.

Operands: not specified.

Opcode: base opcode (toolchain table): 0x0000 (toolchain placeholder, FMT 0x1c; not an independent machine encoding in this table). Bit field row: not specified (outside the provided range).

Status bits: not specified.

Words / Cycles: not specified.

Cycle class: see Instruction Timing.

Example: not specified.

RHM

Reset hold mode (CLRC-mode alias).

Description: Not specified. The descriptive entry for RHM is outside the provided SPRU056D range; only the toolchain opcode is available here.

Syntax: not specified.

Operation: not specified.

Operands: not specified.

Opcode: base opcode (toolchain table): 0xBE48 (FMT 0x1c). Bit field row: not specified (outside the provided range).

Status bits: not specified.

Words / Cycles: not specified.

Cycle class: see Instruction Timing.

Example: not specified.

ROL

Rotate the accumulator left one bit through the carry.

Syntax: ROL

Operation: (PC) + 1 -> PC; C -> ACC(0); ACC(31) -> C; ACC(30-0) -> ACC(31-1).

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  0  0  1  1  0  0   = 0xBE0C

Base opcode (toolchain table): 0xBE0C.

Status bits: Not affected by SXM. Affects C.

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: ROL

ROLB

Rotate the accumulator and accumulator buffer left one bit (65-bit rotation) through the carry.

Syntax: ROLB

Operation: (PC) + 1 -> PC; C -> ACCB(0); ACCB(30-0) -> ACCB(31-1); ACCB(31) -> ACC(0); ACC(30-0) -> ACC(31-1); ACC(31) -> C.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  0  1  0  1  0  0   = 0xBE14

Base opcode (toolchain table): 0xBE14.

Status bits: Not affected by SXM. Affects C.

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: ROLB

ROR

Rotate the accumulator right one bit through the carry.

Syntax: ROR

Operation: (PC) + 1 -> PC; C -> ACC(31); ACC(0) -> C; ACC(31-1) -> ACC(30-0).

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  0  0  1  1  0  1   = 0xBE0D

Base opcode (toolchain table): 0xBE0D.

Status bits: Not affected by SXM. Affects C.

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycle Timings for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: ROR

RORB

Rotate the accumulator and accumulator buffer right one bit (65-bit rotation) through the carry.

Syntax: RORB

Operation: (PC) + 1 -> PC; C -> ACC(31); ACC(31-1) -> ACC(30-0); ACC(0) -> ACCB(31); ACCB(31-1) -> ACCB(30-0); ACCB(0) -> C.

Operands: None.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   0  0  0  1  0  1  0  1   = 0xBE15

Base opcode (toolchain table): 0xBE15.

Status bits: Not affected by SXM. Affects C.

Words / Cycles: 1 word; 1 cycle (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	1	1	1	1+p
Cycles for a Repeat (RPT) Execution	n	n	n	n+p

Example: RORB

ROVM

Reset overflow mode (CLRC-mode alias).

Description: Not specified. The descriptive entry for ROVM is outside the provided SPRU056D range; only the toolchain opcode is available here.

Syntax: not specified.

Operation: not specified.

Operands: not specified.

Opcode: base opcode (toolchain table): 0xBE42. Bit field row: not specified (outside the provided range).

Status bits: not specified.

Words / Cycles: not specified.

Cycle class: see Instruction Timing.

Example: not specified.

RPT

Repeat the next instruction (count+1) times.

Syntax: RPT dma (direct); RPT {ind} [,ARn] (indirect); RPT #k (short immediate); RPT #lk (long immediate). The encoding forms are RPTI (direct/indirect), RPTK (short immediate), and RPTR (long immediate).

Operation: Direct/indirect: (PC) + 1 -> PC, (dma) -> RPTC. Short immediate: (PC) + 1 -> PC, k -> RPTC. Long immediate: (PC) + 2 -> PC, lk -> RPTC. The following instruction runs n times, n = initial RPTC + 1.

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= k <= 255; 0 <= lk <= 65535; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  0  0  0  1  0  1  1   0  [            dma           ]    direct    (0x0B00)
  0  0  0  0  1  0  1  1   1  [ indirect: see Section 5.2 ]   indirect
  1  0  1  1  1  0  1  1   [        8-bit constant      ]      short immediate (0xBB00)
  1  0  1  1  1  1  1  0   1  1  0  0  0  1  0  0            long immediate  (0xBEC4)
                              [ 16-bit constant in second word for long immediate ]

Base opcode (toolchain table): 0x0001 (toolchain repeat format-group base, FMT 0x20; per-form encodings are 0x0B00 for RPTI, 0xBB00 for RPTK, 0xBEC4 for RPTR).

Status bits: None affected. Repeat loops are not interruptible; the RPTC is cleared on reset.

Words / Cycles: 1 word (direct, indirect, or short immediate) or 2 words (long immediate); 1 cycle (direct/indirect, DARAM) or 2 cycles (immediate). Not repeatable.

Cycle class: IIA (RPT); XXIX (RPT #k); III (RPT #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RPT instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2*	1+p
External	1+d	1+d	1+d	2+d+p

* If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (immediate addressing)

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	2	2	2	2+2p

Example: RPT #1 ; repeat the next instruction twice

RPTB

Repeat a block of instructions without loop overhead.

Syntax: RPTB pma

Operation: 1 -> BRAF; (PC) + 2 -> PASR; pma -> PAER. The BRCR must be loaded first; iteration count is (BRCR) + 1.

Operands: 0 <= pma <= 65535.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   1  1  0  0  0  1  1  0   = 0xBEC6
                              [ 16-bit constant in second word ]

Base opcode (toolchain table): 0xBEC6.

Status bits: Affected by BRAF. Affects BRAF. The repeat block must contain at least three instruction words.

Words / Cycles: 2 words; 2 cycles (single; not repeatable).

Cycle class: III - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RPTB instruction is not repeatable.

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	2	2	2	2+2p

Example: RPTB end_block-1

RPTI

RPT encoding form: load the repeat counter from data memory (direct/indirect).

Syntax: RPT dma (direct); RPT {ind} [,ARn] (indirect). This is the direct/indirect form of RPT.

Operation: (PC) + 1 -> PC; (dma) -> RPTC. The following instruction runs (RPTC)+1 times.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  0  0  0  0  1  0  1  1   0  [            dma           ]    direct    (0x0B00)
  0  0  0  0  1  0  1  1   1  [ indirect: see Section 5.2 ]   indirect

Base opcode (toolchain table): 0x0B00.

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single, DARAM). Not repeatable.

Cycle class: see Instruction Timing.

Example: RPT DAT127

RPTK

RPT encoding form: load the repeat counter from an 8-bit immediate.

Syntax: RPT #k. This is the short-immediate form of RPT.

Operation: (PC) + 1 -> PC; k -> RPTC. The following instruction runs k+1 times.

Operands: 0 <= k <= 255.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  0  1  1   [        8-bit constant k     ]    = 0xBB00 | k

Base opcode (toolchain table): 0xBB00.

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: RPT #1

RPTR

RPT encoding form: load the repeat counter from a 16-bit long immediate.

Syntax: RPT #lk. This is the long-immediate form of RPT.

Operation: (PC) + 2 -> PC; lk -> RPTC. The following instruction runs lk+1 times.

Operands: 0 <= lk <= 65535.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   1  1  0  0  0  1  0  0   = 0xBEC4
                              [ 16-bit constant in second word ]

Base opcode (toolchain table): 0xBEC4.

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: RPT #1111h

RPTZ

Clear ACC and PREG, then repeat the next instruction (lk+1) times.

Syntax: RPTZ #lk

Operation: 0 -> ACC; 0 -> PREG; (PC) + 1 -> PC; lk -> RPTC. Equivalent to MPY #0 / PAC / RPT #lk.

Operands: 0 <= lk <= 65535.

Opcode:

 15 14 13 12 11 10  9  8   7  6  5  4  3  2  1  0
  1  0  1  1  1  1  1  0   1  1  0  0  0  1  0  1   = 0xBEC5
                              [ 16-bit constant in second word ]

Base opcode (toolchain table): 0xBEC5.

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single; not repeatable).

Cycle class: III (RPTZ #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The RPTZ instruction is not repeatable.

	ROM	DARAM	SARAM	External Memory
Cycles for a Single Instruction	2	2	2	2+2p

Example: RPTZ #7FFh

RSXM

Reset sign-extension mode (CLRC-mode alias).

Description: Not specified. The descriptive entry for RSXM is outside the provided SPRU056D range; only the toolchain opcode is available here.

Syntax: not specified.

Operation: not specified.

Operands: not specified.

Opcode: base opcode (toolchain table): 0xBE46. Bit field row: not specified (outside the provided range).

Status bits: not specified.

Words / Cycles: not specified.

Cycle class: see Instruction Timing.

Example: not specified.

RTC

Reset the test/control (TC) bit (CLRC-mode alias).

Description: Not specified. The descriptive entry for RTC is outside the provided SPRU056D range; only the toolchain opcode is available here.

Syntax: not specified.

Operation: not specified.

Operands: not specified.

Opcode: base opcode (toolchain table): 0xBE4A. Bit field row: not specified (outside the provided range).

Status bits: not specified.

Words / Cycles: not specified.

Cycle class: see Instruction Timing.

Example: not specified.

RTXM

Reset serial-port transmit mode (CLRC-mode alias).

Description: Not specified. The descriptive entry for RTXM is outside the provided SPRU056D range; only the toolchain opcode is available here.

Syntax: not specified.

Operation: not specified.

Operands: not specified.

Opcode: base opcode (toolchain table): 0x0000 (toolchain placeholder, FMT 0x1c; not an independent machine encoding in this table). Bit field row: not specified (outside the provided range).

Status bits: not specified.

Words / Cycles: not specified.

Cycle class: see Instruction Timing.

Example: not specified.

RXF

Reset the external-flag (XF) pin (CLRC-mode alias).

Description: Not specified. The descriptive entry for RXF is outside the provided SPRU056D range; only the toolchain opcode is available here.

Syntax: not specified.

Operation: not specified.

Operands: not specified.

Opcode: base opcode (toolchain table): 0xBE4C. Bit field row: not specified (outside the provided range).

Status bits: not specified.

Words / Cycles: not specified.

Cycle class: see Instruction Timing.

Example: not specified.

SACB

Copy the accumulator into the accumulator buffer.

Syntax: SACB

Operation: (PC) + 1 -> PC; (ACC) -> ACCB

Operands: None.

Opcode: 1011 1110 0001 1110 ; base 0xBE1E

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SACB ; ACCB <- ACC, ACC unchanged.

SACH

Shift the accumulator left 0 to 7 bits and store the high word to data memory.

Syntax: Direct: SACH dma [,shift2] ; Indirect: SACH {ind} [,shift2[,ARn]]

Operation: (PC) + 1 -> PC; high word of ((ACC) x 2^shift2) -> dma (ACC unchanged)

Operands: 0 <= dma <= 127; 0 <= shift2 <= 7 (defaults to 0); 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    1 0 0 1 1 [SHF] 0 [dma 7]           base 0x9800
Indirect:  1 0 0 1 1 [SHF] 1 [indirect field]

Status bits: Not affected by SXM.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IVA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	2+d	2+d	2+d	4+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+2 [a]	n+p
External	2n+nd	2n+nd	2n+nd	2n+2+nd+p

[a] If the operand and the code are in the same SARAM block

Example: SACH DAT10,1 ; store ACC high word after a 1-bit left shift.

SACL

Shift the accumulator low word left 0 to 7 bits and store it to data memory.

Syntax: Direct: SACL dma [,shift2] ; Indirect: SACL {ind} [,shift2[,ARn]]

Operation: (PC) + 1 -> PC; (ACC(15-0)) x 2^shift2 -> dma (low-order bits zero-filled, high-order bits lost)

Operands: 0 <= dma <= 127; 0 <= shift2 <= 7 (defaults to 0); 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    1 0 0 1 0 [SHF] 0 [dma 7]           base 0x9000
Indirect:  1 0 0 1 0 [SHF] 1 [indirect field]

Status bits: Not affected by SXM.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IVA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	2+d	2+d	2+d	4+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+2 [a]	n+p
External	2n+nd	2n+nd	2n+nd	2n+2+nd+p

[a] If the operand and the code are in the same SARAM block

Example: SACL DAT11,1 ; store ACC low word after a 1-bit left shift.

SAMM

Store the accumulator low word to a memory-mapped register on page 0.

Syntax: Direct: SAMM dma ; Indirect: SAMM {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC(15-0)) -> dma(0-7) (the 9 MSBs of the address are forced to 0, DP unchanged)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    1 0 0 0 1 0 0 0 0 [dma 7]           base 0x8800
Indirect:  1 0 0 0 1 0 0 0 1 [indirect field]

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single execution, memory-mapped register operand).

Cycle class: IVB - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
MMR [a]	1	1	1	1+p
MMPORT	2+iodst	2+iodst	2+iodst	4+iodst

[a] Add one more cycle if source is a peripheral memory-mapped register access

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
MMR [b]	n	n	n	n+p
MMPORT	2+niodst	2+niodst	2+niodst	2n+2+p+p niodst

[b] Add n more cycles if source is a peripheral memory-mapped register access

Example: SAMM PRD ; store ACC low word to the period register without touching DP.

SAR

Store an auxiliary register to data memory.

Syntax: Direct: SAR ARx, dma ; Indirect: SAR ARx, {ind} [,ARn]

Operation: (PC) + 1 -> PC; (AR) -> dma (in indirect mode the pre-modify AR value is stored)

Operands: 0 <= dma <= 127; 0 <= x <= 7; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    1 0 0 0 0 [ARX] 0 [dma 7]           base 0x8000
Indirect:  1 0 0 0 0 [ARX] 1 [indirect field]

Status bits: Affected by NDX.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IVA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	2+d	2+d	2+d	4+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+2 [a]	n+p
External	2n+nd	2n+nd	2n+nd	2n+2+nd+p

[a] If the operand and the code are in the same SARAM block

Example: SAR AR0,DAT30 ; store AR0 to data memory.

SATH

Barrel-shift the accumulator right by 16 bits when TREG1 bit 4 is set.

Syntax: SATH

Operation: (PC) + 1 -> PC; count = 16 x TREG1(4); (ACC) right-shifted by count -> ACC

Operands: None.

Opcode: 1011 1110 0101 1010 ; base 0xBE5A

Status bits: Affected by SXM; does not affect C. If SXM is cleared the vacated high bits are zero-filled, otherwise they are filled with ACC bit 31.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SATH ; with TREG1 bit 4 set, ACC is shifted right 16 bits.

SATL

Barrel-shift the accumulator right by the count held in the four LSBs of TREG1.

Syntax: SATL

Operation: (PC) + 1 -> PC; count = TREG1(3-0); (ACC) right-shifted by count -> ACC

Operands: None.

Opcode: 1011 1110 0101 1011 ; base 0xBE5B

Status bits: Affected by SXM; does not affect C. SXM cleared zero-fills the high bits, SXM set copies ACC bit 31 into them. Together with SATH it forms a 2-cycle 0 to 31 bit right shift.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SATL ; with TREG1 = x2h, ACC is shifted right 2 bits.

SBB

Subtract the accumulator buffer from the accumulator.

Syntax: SBB

Operation: (PC) + 1 -> PC; (ACC) - (ACCB) -> ACC

Operands: None.

Opcode: 1011 1110 0001 1000 ; base 0xBE18

Status bits: Affects C. C is cleared if the subtraction generates a borrow, otherwise it is set. ACCB is unchanged.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SBB ; ACC <- ACC - ACCB.

SBBB

Subtract the accumulator buffer and the logical inversion of C from the accumulator.

Syntax: SBBB

Operation: (PC) + 1 -> PC; (ACC) - (ACCB) - (logical inversion of C) -> ACC

Operands: None.

Opcode: 1011 1110 0001 1001 ; base 0xBE19

Status bits: Affects C. C is cleared if the subtraction generates a borrow, otherwise it is set. ACCB is unchanged.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SBBB ; borrow-aware subtract of ACCB from ACC.

SBLK

Subtract a 16-bit long immediate, shifted, from the accumulator. This is the long-immediate form of SUB (see SUB).

Syntax: SBLK #lk [,shift]

Operation: (PC) + 2 -> PC; (ACC) - (lk x 2^shift) -> ACC

Operands: -32768 <= lk <= 32767; 0 <= shift <= 16 (defaults to 0)

Opcode:

Word 1:  1 0 1 1 1 1 1 1 1 0 1 0 [SHFT 4]      base 0xBFA0
Word 2:  [16-bit constant]

Status bits: Affected by OVM and SXM; affects C and OV.

Words / Cycles: 2 words; 2 cycles (single execution, long immediate).

Cycle class: see Instruction Timing.

Example: SBLK #01234h,4 ; subtract the shifted long immediate from ACC.

SBRK

Subtract an 8-bit positive immediate from the current auxiliary register.

Syntax: SBRK #k

Operation: (PC) + 1 -> PC; (current AR) - k -> current AR (performed in the ARAU, k treated as 8-bit positive)

Operands: 0 <= k <= 255

Opcode: 0 1 1 1 1 1 0 0 [8-bit constant] ; base 0x7C00

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM). SBRK is not repeatable.

Cycle class: I (SBRK #k) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The SBRK instruction is not repeatable.

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Example: SBRK #0FFh ; current AR <- current AR - 0FFh.

SC

Set the carry bit. This is the single-bit form of SETC C (see SETC).

Syntax: SC

Operation: (PC) + 1 -> PC; 1 -> C

Operands: None.

Opcode: 1011 1110 0100 1111 ; base 0xBE4F

Status bits: Affects C (sets it).

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: see Instruction Timing.

Example: SC ; C <- 1.

SETC

Set a named control bit in the status registers.

Syntax: SETC control bit

Operation: (PC) + 1 -> PC; 1 -> control bit

Operands: control bit: {C, CNF, HM, INTM, OVM, SXM, TC, XF}

Opcode: Shared pattern 1 0 1 1 1 1 1 0 0 1 0 0 [4-bit bit select]. Per-bit opcode words from the manual:

SETC INTM  1011 1110 0100 0001   0xBE41
SETC OVM   1011 1110 0100 0011   0xBE43
SETC CNF   1011 1110 0100 0101   0xBE45
SETC SXM   1011 1110 0100 0111   0xBE47
SETC HM    1011 1110 0100 1001   0xBE49
SETC TC    1011 1110 0100 1011   0xBE4B
SETC XF    1011 1110 0100 1101   0xBE4D
SETC C     1011 1110 0100 1111   0xBE4F

Toolchain generic base 0x0001. (See SC, SHM, SOVM, SSXM, STC, SXF for the standalone equivalents.)

Status bits: Affects the selected control bit.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SETC TC ; TC (bit 11 of ST1) is set. Note: an IDLE must not immediately follow SETC INTM.

SFL

Shift the accumulator left 1 bit through the carry.

Syntax: SFL

Operation: (PC) + 1 -> PC; (ACC(31)) -> C; (ACC(30-0)) -> ACC(31-1); 0 -> ACC(0)

Operands: None.

Opcode: 1011 1110 0000 1001 ; base 0xBE09

Status bits: Not affected by SXM; affects C. Unlike SFR, SFL ignores SXM.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SFL ; ACC <- ACC << 1, MSB into C, LSB zero-filled.

SFLB

Shift the accumulator and the accumulator buffer left 1 bit as a 64-bit field.

Syntax: SFLB

Operation: (PC) + 1 -> PC; 0 -> ACCB(0); (ACCB(30-0)) -> ACCB(31-1); (ACCB(31)) -> ACC(0); (ACC(30-0)) -> ACC(31-1); (ACC(31)) -> C

Operands: None.

Opcode: 1011 1110 0001 0110 ; base 0xBE16

Status bits: Not affected by SXM; affects C. Unlike SFRB, SFLB ignores SXM.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SFLB ; ACC:ACCB shifted left 1 bit, ACC MSB into C.

SFR

Shift the accumulator right 1 bit, logical or arithmetic per SXM.

Syntax: SFR

Operation: (PC) + 1 -> PC; if SXM = 0: 0 -> ACC(31); if SXM = 1: (ACC(31)) -> ACC(31); (ACC(31-1)) -> ACC(30-0); (ACC(0)) -> C

Operands: None.

Opcode: 1011 1110 0000 1010 ; base 0xBE0A

Status bits: Affected by SXM; affects C. SXM cleared gives a logical right shift (MSB zero-filled), SXM set gives an arithmetic right shift (sign preserved).

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SFR ; ACC <- ACC >> 1, LSB into C.

SFRB

Shift the accumulator and the accumulator buffer right 1 bit as a 64-bit field.

Syntax: SFRB

Operation: (PC) + 1 -> PC; if SXM = 0: 0 -> ACC(31); if SXM = 1: (ACC(31)) -> ACC(31); (ACC(31-1)) -> ACC(30-0); (ACC(0)) -> ACCB(31); (ACCB(31-1)) -> ACCB(30-0); (ACCB(0)) -> C

Operands: None.

Opcode: 1011 1110 0001 0111 ; base 0xBE17

Status bits: Affected by SXM; affects C. SXM cleared zero-fills the ACC MSB, SXM set preserves the sign.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SFRB ; ACC:ACCB shifted right 1 bit, ACCB LSB into C.

SFSM

Set the frame-synchronization control bit (toolchain-recognized single-bit set mnemonic).

Syntax: not specified (no entry in the SPRU056D chapter 6 S-instruction range)

Operation: not specified in source range

Operands: not specified in source range

Opcode: base 0x0000 (toolchain table; no opcode word given in the source range)

Status bits: not specified in source range

Words / Cycles: not specified in source range

Cycle class: see Instruction Timing.

Example: not specified in source range

SHM

Set the hold mode bit. This is the single-bit form of SETC HM (see SETC).

Syntax: SHM

Operation: (PC) + 1 -> PC; 1 -> HM

Operands: None.

Opcode: 1011 1110 0100 1001 ; base 0xBE49

Status bits: Affects HM (sets it).

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: see Instruction Timing.

Example: SHM ; HM <- 1.

SMMR

Store a memory-mapped register to any data-memory location.

Syntax: Direct: SMMR dma, #addr ; Indirect: SMMR {ind}, #addr [,ARn]

Operation: PFC -> MCS; (PC) + 2 -> PC; lk -> PFC; while repeat counter != 0: (src = low 7 bits of dma) -> (dst addressed by PFC); (PFC) + 1 -> PFC; (repeat counter) - 1 -> repeat counter; MCS -> PFC. The 9 MSBs of the dma are forced to 0 (DP unchanged); with RPT the destination #addr auto-increments.

Operands: 0 <= addr <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Word 1 direct:    0 0 0 0 1 0 0 1 0 [dma 7]       base 0x0900
Word 1 indirect:  0 0 0 0 1 0 0 1 1 [indirect field]
Word 2:           [16-bit constant #addr]

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution, DARAM destination with MMR source).

Cycle class: XXIV - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
Destination: DARAM, Source: MMR [b]	2	2	2	2+2pcode
Destination: SARAM, Source: MMR [b]	2	2	2, 3 [a]	2+2pcode
Destination: External, Source: MMR [b]	3+ddst	3+ddst	3+ddst	5+ddst +2pcode
Destination: DARAM, Source: MMPORT	3+iosrc	3+iosrc	3+iosrc	4+iosrc +2pcode
Destination: SARAM, Source: MMPORT	3+iosrc	3+iosrc	3+iosrc , 4+iosrc [a]	3+iosrc +2pcode
Destination: External, Source: MMPORT	4+iosrc +ddst	4+iosrc +ddst	4+iosrc +ddst	6+iosrc +ddst +2pcode

[a] If the destination operand and the code are in the same SARAM block [b] Add one more cycle for peripheral memory-mapped register access.

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
Destination: DARAM, Source: MMR [c]	2n	2n	2n	2n+2pcode
Destination: SARAM, Source: MMR [c]	2n	2n	2n, 2n+2 [a]	2n+2pcode
Destination: External, Source: MMR [c]	3n+nddst	3n+nddst	3n+nddst	3n+3+nddst +2pcode
Destination: DARAM, Source: MMPORT	2n+niosrc	2n+niosrc	2n+niosrc	2n+1+niosrc +2pcode
Destination: SARAM, Source: MMPORT	2n+niosrc	2n+niosrc	2n+niosrc , 2n+2+niosrc [a]	2n+1+niosrc +2pcode
Destination: External, Source: MMPORT	5n-2+nddst +niosrc	5n-2+nddst +niosrc	5n-2+nddst +niosrc	5n+1+nddst +niosrc +2pcode

[a] If the destination operand and the code are in the same SARAM block [c] Add n more cycles for peripheral memory-mapped register access.

Example: SMMR CBCR,#307h ; copy the circular-buffer control register to data memory 307h.

SOVM

Set the overflow mode bit. This is the single-bit form of SETC OVM (see SETC).

Syntax: SOVM

Operation: (PC) + 1 -> PC; 1 -> OVM

Operands: None.

Opcode: 1011 1110 0100 0011 ; base 0xBE43

Status bits: Affects OVM (sets it).

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: see Instruction Timing.

Example: SOVM ; OVM <- 1.

SPAC

Subtract the shifted product register from the accumulator.

Syntax: SPAC

Operation: (PC) + 1 -> PC; (ACC) - (shifted PREG) -> ACC

Operands: None.

Opcode: 1011 1110 0000 0101 ; base 0xBE05

Status bits: Affected by OVM and PM; not affected by SXM; affects C and OV. C is cleared on a borrow, otherwise set. PREG is always sign-extended. SPAC is a subset of LTS, MPYS, and SQRS.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p

Example: SPAC ; ACC <- ACC - (PREG shifted by PM).

SPH

Store the shifted product-register high word to data memory.

Syntax: Direct: SPH dma ; Indirect: SPH {ind} [,ARn]

Operation: (PC) + 1 -> PC; (PREG shifter output(31-16)) -> dma (PREG and ACC unchanged)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    1 0 0 0 1 1 0 1 0 [dma 7]           base 0x8D00
Indirect:  1 0 0 0 1 1 0 1 1 [indirect field]

Status bits: Affected by PM. With right-shift-by-6 mode the high bits are sign extended; with left shifts the low bits are filled from the PREG low word.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IVA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	2+d	2+d	2+d	4+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+2 [a]	n+p
External	2n+nd	2n+nd	2n+nd	2n+2+nd+p

[a] If the operand and the code are in the same SARAM block

Example: SPH DAT3 ; store the PREG high word per the PM shift.

SPL

Store the shifted product-register low word to data memory.

Syntax: Direct: SPL dma ; Indirect: SPL {ind} [,ARn]

Operation: (PC) + 1 -> PC; (PREG shifter output(15-0)) -> dma (PREG and ACC unchanged)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    1 0 0 0 1 1 0 0 0 [dma 7]           base 0x8C00
Indirect:  1 0 0 0 1 1 0 0 1 [indirect field]

Status bits: Affected by PM. With right-shift-by-6 mode the high bits are filled from the PREG high word; with left shifts the low bits are zero-filled.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IVA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	2+d	2+d	2+d	4+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+2 [a]	n+p
External	2n+nd	2n+nd	2n+nd	2n+2+nd+p

[a] If the operand and the code are in the same SARAM block

Example: SPL DAT5 ; store the PREG low word per the PM shift.

SPLK

Store a 16-bit long immediate into data memory via the parallel logic unit.

Syntax: Direct: SPLK #lk, dma ; Indirect: SPLK #lk, {ind} [,ARn]

Operation: (PC) + 2 -> PC; lk -> dma (ACC unchanged; performed by the PLU)

Operands: 0 <= dma <= 127; 0 <= n <= 7; lk: 16-bit constant; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Word 1 direct:    1 0 1 0 1 1 1 0 0 [dma 7]       base 0xAE00
Word 1 indirect:  1 0 1 0 1 1 1 0 1 [indirect field]
Word 2:           [16-bit constant lk]

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution, DARAM operand). SPLK is not repeatable.

Cycle class: VIIb - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The SPLK instruction is not repeatable.

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	2	2	2	2+2p
SARAM	2	2	2, 3 [a]	2+2p
External	3+d	3+d	3+d	5+d+2p

[a] If the operand and the code are in the same SARAM block

Example: SPLK #7FFFh,DAT3 ; write 7FFFh to the addressed data word.

SPM

Set the product shift mode bits in ST1.

Syntax: SPM constant

Operation: (PC) + 1 -> PC; constant -> PM

Operands: 0 <= constant <= 3

Opcode: 1 0 1 1 1 1 1 1 0 0 0 0 0 0 [PM 2] ; base 0xBF00

Status bits: Not affected by SXM; affects PM. PM = 00 no shift, 01 left 1 (LSB zero-filled), 10 left 4 (4 LSBs zero-filled), 11 right 6 (sign extended, 6 LSBs lost).

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM). SPM is not repeatable.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The SPM instruction is not repeatable.

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Example: SPM 3 ; select product shift mode 3 (right shift by 6).

SQRA

Square a data value into PREG and add the previous shifted product to the accumulator.

Syntax: Direct: SQRA dma ; Indirect: SQRA {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + (shifted PREG) -> ACC; (dma) -> TREG0; (dma) x (dma) -> PREG; if TRM = 0: (dma) -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    0 1 0 1 0 0 1 0 0 [dma 7]           base 0x5200
Indirect:  0 1 0 1 0 0 1 0 1 [indirect field]

Status bits: Affected by OVM, PM, and TRM; affects C and OV. C is set on a carry from the addition, otherwise cleared.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Example: SQRA DAT30 ; accumulate the old product, then square Data(DAT30) into PREG.

SQRS

Square a data value into PREG and subtract the previous shifted product from the accumulator.

Syntax: Direct: SQRS dma ; Indirect: SQRS {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) - (shifted PREG) -> ACC; (dma) -> TREG0; (dma) x (dma) -> PREG; if TRM = 0: (dma) -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    0 1 0 1 0 0 1 1 0 [dma 7]           base 0x5300
Indirect:  0 1 0 1 0 0 1 1 1 [indirect field]

Status bits: Affected by OVM, PM, and TRM; affects C and OV. C is cleared on a borrow from the subtraction, otherwise set.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Example: SQRS DAT9 ; subtract the old product, then square Data(DAT9) into PREG.

SST

Store a status register (ST0 or ST1) to data memory.

Syntax: Direct: SST #m, dma ; Indirect: SST #m, {ind} [,ARn]

Operation: (PC) + 1 -> PC; (STm) -> dma. In direct mode the store always targets data page 0 (DP is not physically modified); in indirect mode any page may be addressed.

Operands: 0 <= dma <= 127; m = 0 or 1; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

#0 direct:    1 0 0 0 1 1 1 0 0 [dma 7]        base 0x8E00
#0 indirect:  1 0 0 0 1 1 1 0 1 [indirect field]
#1 direct:    1 0 0 0 1 1 1 1 0 [dma 7]        base 0x8F00
#1 indirect:  1 0 0 0 1 1 1 1 1 [indirect field]

Toolchain generic base 0x0001. (See SST0 and SST1 for the fixed-register forms.)

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IVA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	2+d	2+d	2+d	4+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+2 [a]	n+p
External	2n+nd	2n+nd	2n+nd	2n+2+nd+p

[a] If the operand and the code are in the same SARAM block

Example: SST #0,DAT96 ; store ST0 to data page 0.

SST0

Store status register ST0 to data memory. This is the #0 form of SST (see SST).

Syntax: Direct: SST0 dma ; Indirect: SST0 {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ST0) -> dma (direct mode targets data page 0, DP not physically modified)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    1 0 0 0 1 1 1 0 0 [dma 7]           base 0x8E00
Indirect:  1 0 0 0 1 1 1 0 1 [indirect field]

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: see Instruction Timing.

Example: SST0 DAT96 ; store ST0 to data page 0.

SST1

Store status register ST1 to data memory. This is the #1 form of SST (see SST).

Syntax: Direct: SST1 dma ; Indirect: SST1 {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ST1) -> dma (direct mode targets data page 0, DP not physically modified)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    1 0 0 0 1 1 1 1 0 [dma 7]           base 0x8F00
Indirect:  1 0 0 0 1 1 1 1 1 [indirect field]

Status bits: None affected.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: see Instruction Timing.

Example: SST1 *,AR7 ; store ST1 via the current AR.

SSXM

Set the sign-extension mode bit. This is the single-bit form of SETC SXM (see SETC).

Syntax: SSXM

Operation: (PC) + 1 -> PC; 1 -> SXM

Operands: None.

Opcode: 1011 1110 0100 0111 ; base 0xBE47

Status bits: Affects SXM (sets it).

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: see Instruction Timing.

Example: SSXM ; SXM <- 1.

STC

Set the test/control bit. This is the single-bit form of SETC TC (see SETC).

Syntax: STC

Operation: (PC) + 1 -> PC; 1 -> TC

Operands: None.

Opcode: 1011 1110 0100 1011 ; base 0xBE4B

Status bits: Affects TC (sets it).

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: see Instruction Timing.

Example: STC ; TC (bit 11 of ST1) <- 1.

STXM

Set the transmit-mode control bit (toolchain-recognized single-bit set mnemonic).

Syntax: not specified (no entry in the SPRU056D chapter 6 S-instruction range)

Operation: not specified in source range

Operands: not specified in source range

Opcode: base 0x0000 (toolchain table; no opcode word given in the source range)

Status bits: not specified in source range

Words / Cycles: not specified in source range

Cycle class: see Instruction Timing.

Example: not specified in source range

SUB

Subtract a data-memory value or a constant, optionally shifted, from the accumulator.

Syntax: Direct: SUB dma [,shift] ; Indirect: SUB {ind} [,shift[,ARn]] ; Short immediate: SUB #k ; Long immediate: SUB #lk [,shift]

Operation: Direct/indirect: (PC) + 1 -> PC; (ACC) - ((dma) x 2^shift) -> ACC. Short immediate: (PC) + 1 -> PC; (ACC) - k -> ACC. Long immediate: (PC) + 2 -> PC; (ACC) - (lk x 2^shift) -> ACC. During shifts the ACC low byte is zero-filled; SXM controls high-bit fill.

Operands: 0 <= dma <= 127; 0 <= shift <= 16 (defaults to 0); 0 <= n <= 7; 0 <= k <= 255; -32768 <= lk <= 32767; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct w/ shift:       0 0 1 1 [SHFT] 0 [dma 7]          base 0x3000 (see SUBI)
Indirect w/ shift:     0 0 1 1 [SHFT] 1 [indirect field]
Direct shift of 16:    0 1 1 0 0 1 0 1 0 [dma 7]         base 0x6500 (see SUBH)
Short immediate:       1 0 1 1 1 0 1 0 [8-bit const]     base 0xBA00 (see SUBK)
Long immediate w/shift:1 0 1 1 1 1 1 1 1 0 1 0 [SHFT 4] + word2 const   base 0xBFA0 (see SBLK)

Toolchain generic base 0x0002.

Status bits: Affected by OVM (and SXM for direct/indirect/long immediate); affects C and OV. C is cleared on a borrow; with a shift of 16 C is only cleared on a borrow and otherwise unaffected.

Words / Cycles: 1 word (direct, indirect, short immediate) or 2 words (long immediate); 1 cycle (single execution, direct/indirect, DARAM) or 2 cycles (long immediate). Short and long immediate forms are not repeatable.

Cycle class: IIA (SUB); I (SUB #k); III (SUB #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short and long immediate addressing modes, the SUB instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Single Instruction (long immediate addressing)

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p

Example: SUB DAT80 ; ACC <- ACC - Data(DAT80).

SUBB

Subtract a data value and the logical inversion of C from the accumulator.

Syntax: Direct: SUBB dma ; Indirect: SUBB {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) - (dma) - (logical inversion of C) -> ACC (sign extension suppressed)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    0 1 1 0 0 1 0 0 0 [dma 7]           base 0x6400
Indirect:  0 1 1 0 0 1 0 0 1 [indirect field]

Status bits: Affected by OVM; not affected by SXM; affects C and OV. Used for multiple-precision arithmetic.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Example: SUBB DAT5 ; borrow-aware subtract of Data(DAT5) from ACC.

SUBC

Conditional subtract used as a divide step.

Syntax: Direct: SUBC dma ; Indirect: SUBC {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) - ((dma) x 2^15) -> ALU output; if ALU output >= 0: (ALU output) x 2 + 1 -> ACC; else: (ACC) x 2 -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    0 0 0 0 1 0 1 0 0 [dma 7]           base 0x0A00
Indirect:  0 0 0 0 1 0 1 0 1 [indirect field]

Status bits: Not affected by OVM (no saturation) or SXM; affects C and OV. Execute 16 times for a 16-bit divide; quotient ends in ACCL, remainder in ACCH.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Example: RPT #15 then SUBC * ; a 16-bit division step repeated 16 times.

SUBH

Subtract a data value shifted left 16 bits (into the accumulator high word). This is the shift-of-16 form of SUB (see SUB).

Syntax: Direct: SUBH dma ; Indirect: SUBH {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) - ((dma) x 2^16) -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    0 1 1 0 0 1 0 1 0 [dma 7]           base 0x6500
Indirect:  0 1 1 0 0 1 0 1 1 [indirect field]

Status bits: Affected by OVM and SXM; affects C and OV. With the shift of 16, C is cleared only on a borrow and otherwise unaffected.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: see Instruction Timing.

Example: SUBH DAT1 ; subtract Data(DAT1) from the ACC high word.

SUBI

Subtract a data value shifted by a shift code from the accumulator. This is the direct/indirect shifted form of SUB (see SUB).

Syntax: Direct: SUBI dma [,shift] ; Indirect: SUBI {ind} [,shift[,ARn]]

Operation: (PC) + 1 -> PC; (ACC) - ((dma) x 2^shift) -> ACC (ACC low byte zero-filled during the shift; SXM controls high-bit fill)

Operands: 0 <= dma <= 127; 0 <= shift <= 16 (defaults to 0); 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    0 0 1 1 [SHFT] 0 [dma 7]            base 0x3000
Indirect:  0 0 1 1 [SHFT] 1 [indirect field]

Status bits: Affected by OVM and SXM; affects C and OV.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: see Instruction Timing.

Example: SUBI DAT10,4 ; subtract Data(DAT10) shifted left 4 bits from ACC.

SUBK

Subtract an 8-bit short immediate from the accumulator. This is the short-immediate form of SUB (see SUB).

Syntax: SUBK #k

Operation: (PC) + 1 -> PC; (ACC) - k -> ACC (k treated as an 8-bit positive constant, unaffected by SXM)

Operands: 0 <= k <= 255

Opcode: 1 0 1 1 1 0 1 0 [8-bit constant] ; base 0xBA00

Status bits: Affected by OVM; affects C and OV.

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM). Not repeatable.

Cycle class: see Instruction Timing.

Example: SUBK #8h ; ACC <- ACC - 8.

SUBS

Subtract a 16-bit unsigned data value from the accumulator.

Syntax: Direct: SUBS dma ; Indirect: SUBS {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) - (dma) -> ACC with (dma) treated as a 16-bit unsigned number (sign extension suppressed)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    0 1 1 0 0 1 1 0 0 [dma 7]           base 0x6600
Indirect:  0 1 1 0 0 1 1 0 1 [indirect field]

Status bits: Affected by OVM; not affected by SXM; affects C and OV. Equivalent to SUB with SXM cleared and shift 0.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Example: SUBS DAT2 ; subtract the unsigned Data(DAT2) from ACC.

SUBT

Subtract a data value shifted by the four LSBs of TREG1 from the accumulator.

Syntax: Direct: SUBT dma ; Indirect: SUBT {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) - ((dma) x 2^TREG1(3-0)) -> ACC; if SXM = 1 (dma) is sign-extended, if SXM = 0 it is not

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode:

Direct:    0 1 1 0 0 1 1 1 0 [dma 7]           base 0x6700
Indirect:  0 1 1 0 0 1 1 1 1 [indirect field]

Status bits: Affected by OVM, SXM, and TRM; affects C and OV. C is cleared on a borrow, otherwise set.

Words / Cycles: 1 word; 1 cycle (single execution, DARAM operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2 [a]	1+p
External	1+d	1+d	1+d	2+d+p

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1 [a]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[a] If the operand and the code are in the same SARAM block

Example: SUBT DAT127 ; subtract Data(DAT127) shifted by the TREG1 count from ACC.

SWI

Software interrupt (toolchain-recognized mnemonic).

Syntax: not specified (no entry in the SPRU056D chapter 6 S-instruction range)

Operation: not specified in source range

Operands: not specified in source range

Opcode: base 0x0000 (toolchain table; no opcode word given in the source range)

Status bits: not specified in source range

Words / Cycles: not specified in source range

Cycle class: see Instruction Timing.

Example: not specified in source range

SXF

Set the external flag (XF) pin. This is the single-bit form of SETC XF (see SETC).

Syntax: SXF

Operation: (PC) + 1 -> PC; 1 -> XF

Operands: None.

Opcode: 1011 1110 0100 1101 ; base 0xBE4D

Status bits: Affects XF (sets it).

Words / Cycles: 1 word; 1 cycle (single execution, ROM/DARAM/SARAM).

Cycle class: see Instruction Timing.

Example: SXF ; XF pin <- 1.

TBLR

Reads a word from program memory into data memory.

Syntax: TBLR dma (direct); TBLR {ind} [,ARn] (indirect) Operation: (PC) + 1 -> PC; (PFC) -> MCS; (ACC(15-0)) -> PFC; then (pma addressed by PFC) -> dma, modify current AR and ARP as specified; (MCS) -> PFC. The program-memory address comes from the accumulator low byte (ACCL); the data-memory address comes from the instruction. Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: * *+ *- *0+ *0- *BR0+ *BR0- Opcode:

Direct:   1 0 1 0 0 1 1 0 | 0 | dma(7)              -> base 0xA600 (fmt 0x01)
Indirect: 1 0 1 0 0 1 1 0 | 1 | indirect field(7)   (see Addressing Modes)

Status bits: None affected. Words / Cycles: 1 word; 3 cycles for a single execution (source DARAM/ROM, destination DARAM).

Cycle class: XVII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM/ROM, Destination: DARAM	3	3	3	3+pcode
Source: SARAM, Destination: DARAM	3	3	3	3+pcode
Source: External, Destination: DARAM	3+psrc	3+psrc	3+psrc	3+psrc +pcode
Source: DARAM/ROM, Destination: SARAM	3	3	3, 4[1]	3+pcode
Source: SARAM, Destination: SARAM	3	3	3, 4[1]	3+pcode
Source: External, Destination: SARAM	3+psrc	3+psrc	3+psrc , 4+psrc [1]	3+psrc +pcode
Source: DARAM/ROM, Destination: External	4+ddst	4+ddst	4+ddst	6+ddst +pcode
Source: SARAM, Destination: External	4+ddst	4+ddst	4+ddst	6+ddst +pcode
Source: External, Destination: External	4+psrc +ddst	4+psrc +ddst	4+psrc +ddst	6+psrc +ddst +pcode

[1] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM/ROM, Destination: DARAM	n+2	n+2	n+2	n+2+pcode
Source: SARAM, Destination: DARAM	n+2	n+2	n+2	n+2+pcode
Source: External, Destination: DARAM	n+2+npsrc	n+2+npsrc	n+2+npsrc	n+2+npsrc +pcode
Source: DARAM/ROM, Destination: SARAM	n+2	n+2	n+2, n+4[1]	n+2+pcode
Source: SARAM, Destination: SARAM	n+2, 2n[2]	n+2, 2n[2]	n+2, 2n[2], 2n+2[3]	n+2+pcode , 2n[2]
Source: External, Destination: SARAM	n+2+npsrc	n+2+npsrc	n+2+npsrc , n+4+npsrc [1]	n+2+npsrc +pcode
Source: DARAM/ROM, Destination: External	2n+2+nddst	2n+2+nddst	2n+2+nddst	2n+4+nddst +pcode
Source: SARAM, Destination: External	2n+2+nddst	2n+2+nddst	2n+2+nddst	2n+4+nddst +pcode
Source: External, Destination: External	4n+npsrc +nddst	4n+npsrc +nddst	4n+npsrc +nddst	4n+2+npsrc +nddst +pcode

[1] If the destination operand and the code are in the same SARAM block [2] If both the source and the destination operands are in the same SARAM block [3] If both operands and the code are in the same SARAM block Example: TBLR DAT6 reads the program word at the ACCL address into DAT6.

TBLW

Writes a word from data memory into program memory.

Syntax: TBLW dma (direct); TBLW {ind} [,ARn] (indirect) Operation: (PC) + 1 -> PC; (PFC) -> MCS; (ACC(15-0)) -> PFC; then (dma addressed by PFC) -> pma, modify current AR and ARP as specified; (MCS) -> PFC. The data-memory address comes from the instruction; the program-memory address comes from the accumulator low byte (ACCL). Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: * *+ *- *0+ *0- *BR0+ *BR0- Opcode:

Direct:   1 0 1 0 0 1 1 1 | 0 | dma(7)              -> base 0xA700 (fmt 0x01)
Indirect: 1 0 1 0 0 1 1 1 | 1 | indirect field(7)   (see Addressing Modes)

Status bits: None affected. Words / Cycles: 1 word; 3 cycles for a single execution (source DARAM, destination DARAM).

Cycle class: XVIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM, Destination: DARAM	3	3	3	3+pcode
Source: SARAM, Destination: DARAM	3	3	3	3+pcode
Source: External, Destination: DARAM	3+dsrc	3+dsrc	3+dsrc	3+dsrc +pcode
Source: DARAM, Destination: SARAM	3	3	3, 4[1]	3+pcode
Source: SARAM, Destination: SARAM	3	3	3, 4[1]	3+pcode
Source: External, Destination: SARAM	3+dsrc	3+dsrc	3+dsrc , 4+dsrc [1]	3+dsrc +pcode
Source: DARAM, Destination: External	4+pdst	4+pdst	4+pdst	5+pdst +pcode
Source: SARAM, Destination: External	4+pdst	4+pdst	4+pdst	5+pdst +pcode
Source: External, Destination: External	4+dsrc +pdst	4+dsrc +pdst	4+dsrc +pdst	5+dsrc +pdst +pcode

[1] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
Source: DARAM, Destination: DARAM	n+2	n+2	n+2	n+2+pcode
Source: SARAM, Destination: DARAM	n+2	n+2	n+2	n+2+pcode
Source: External, Destination: DARAM	n+2+ndsrc	n+2+ndsrc	n+2+ndsrc	n+2+ndsrc +pcode
Source: DARAM, Destination: SARAM	n+2	n+2	n+2, n+3[1]	n+2+pcode
Source: SARAM, Destination: SARAM	n+2, 2n[2]	n+2, 2n[2]	n+2, 2n[2], 2n+1[3]	n+2+pcode , 2n[2]
Source: External, Destination: SARAM	n+2+ndsrc	n+2+ndsrc	n+2+ndsrc , n+3+ndsrc [1]	n+2+ndsrc +pcode
Source: DARAM, Destination: External	2n+2+npdst	2n+2+npdst	2n+2+npdst	2n+3+npdst +pcode
Source: SARAM, Destination: External	2n+2+npdst	2n+2+npdst	2n+2+npdst	2n+3+npdst +pcode
Source: External, Destination: External	4n+ndsrc +npdst	4n+ndsrc +npdst	4n+ndsrc +npdst	4n+1+ndsrc +npdst +pcode

[1] If the destination operand and the code are in the same SARAM block [2] If both the source and the destination operands are in the same SARAM block [3] If both operands and the code are in the same SARAM block Example: TBLW DAT5 writes DAT5 into the program word at the ACCL address.

TRAP

Software interrupt vectoring through program-memory location 22h.

Syntax: TRAP Operation: (PC) + 1 -> stack; 22h -> PC. The incremented program counter is pushed so a return instruction can pop the address of the instruction after the TRAP. The trap is not maskable. Operands: None. Opcode:

1 0 1 1 1 1 1 0 0 1 0 1 0 0 0 1   -> base 0xBE51 (fmt 0x00)

Status bits: Does not affect INTM and is not affected by INTM. Words / Cycles: 1 word; not repeatable; 4 cycles for a single execution.

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The TRAP instruction is not repeatable.

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
4	4	4	4+3p[1]

[1] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded. Example: TRAP passes control to location 22h and pushes PC + 1 onto the stack.

TRAPD

Not covered by the provided SPRU056D excerpt (lines 19225-20102).

Syntax: not specified Operation: not specified Operands: not specified Opcode: base 0xBE31 (fmt 0x00) from the toolchain table; manual bit-field row not specified. Status bits: not specified Words / Cycles: not specified

Cycle class: see Instruction Timing. Example: not specified

XC

Conditionally executes the next one or two instructions.

Syntax: XC n, cond [,cond1] [,...] Operation: If the condition(s) are met, the next n instructions execute; otherwise n NOPs execute. For n = 1 the following one-word instruction runs; for n = 2 the following one two-word or two one-word instructions run. The XC and the two following instruction words are uninterruptible. Conditions are sampled one full cycle before XC executes. Operands: n = 1 or 2. Conditions: EQ (ACC = 0), NEQ (ACC != 0), LT (ACC < 0), LEQ (ACC <= 0), GT (ACC > 0), GEQ (ACC >= 0), NC (C = 0), C (C = 1), NOV (OV = 0), OV (OV = 1), NTC (TC = 0), TC (TC = 1), BIO (BIO low), UNC (unconditional). Opcode:

1 1 1 N 0 1 | TP(2) | ZLVC(4) | ZLVC(4)   -> base 0xE700 (fmt 0x19)
N = 0 when n = 1, N = 1 when n = 2; TP and ZLVC encode the conditions.

Status bits: None affected. Words / Cycles: 1 word; not repeatable; 1 cycle for a single execution.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The XC instruction is not repeatable.

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p
Example: `XC 1,LEQ,C` executes the next one-word instruction only if ACC <= 0 and the carry bit is set.

XOR

Exclusive-ORs data memory or a long immediate with the accumulator.

Syntax: XOR dma (direct); XOR {ind} [,ARn] (indirect); XOR #lk [,shift] (long immediate) Operation: Direct/indirect: (PC) + 1 -> PC; (ACC(15-0)) XOR (dma) -> ACC(15-0); ACC(31-16) unchanged. Long immediate: (PC) + 2 -> PC; (ACC(31-0)) XOR (lk << shift) -> ACC(31-0). The long immediate is shifted left and zero-extended on both ends. Operands: 0 <= dma <= 127; 0 <= n <= 7; lk: 16-bit constant; 0 <= shift <= 16; ind: * *+ *- *0+ *0- *BR0+ *BR0- Opcode:

Direct:              0 1 1 0 1 1 0 0 | 0 | dma(7)          (0x6C00; see XORI)
Indirect:            0 1 1 0 1 1 0 0 | 1 | indirect(7)     (see XORI)
Long imm + shift:    1 0 1 1 1 1 1 1 1 1 0 1 | SHFT(4)      + 16-bit constant (0xBFD0; see XORK)
Long imm, shift 16:  1 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1        + 16-bit constant (0xBE83)
toolchain group base: 0x0002 (fmt 0x1e)

Status bits: Does not affect C. Long immediate addressing is not affected by SXM. Words / Cycles: 1 word (direct/indirect) or 2 words (long immediate). 1 cycle for a single direct/indirect execution with the operand in DARAM; 2 cycles for long immediate.

Cycle class: IIA (XOR); III (XOR #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the long immediate addressing modes, the XOR instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2[1]	1+p
External	1+d	1+d	1+d	2+d+p

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1[1]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[1] If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing)

ROM	DARAM	SARAM	External Memory
2	2	2	2+2p
Example: `XOR DAT127` exclusive-ORs the data word with ACCL, leaving ACCH unchanged.

XORB

Exclusive-ORs the accumulator with the accumulator buffer.

Syntax: XORB Operation: (PC) + 1 -> PC; (ACC) XOR (ACCB) -> ACC. The result is stored in ACC; ACCB is unchanged. Operands: None. Opcode:

1 0 1 1 1 1 1 0 0 0 0 1 1 0 1 0   -> base 0xBE1A (fmt 0x00)

Status bits: None affected. Words / Cycles: 1 word; 1 cycle for a single execution.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p
Example: `XORB` with ACC = FFFF0000h and ACCB = F0F0F0F0h leaves ACC = 0F0FF0F0h.

XORI

Toolchain mnemonic for the single-word (direct/indirect) form of XOR.

Syntax: XORI dma (direct); XORI {ind} [,ARn] (indirect) Operation: (PC) + 1 -> PC; (ACC(15-0)) XOR (dma) -> ACC(15-0); ACC(31-16) unchanged. Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: * *+ *- *0+ *0- *BR0+ *BR0- Opcode:

Direct:   0 1 1 0 1 1 0 0 | 0 | dma(7)            -> base 0x6C00 (fmt 0x01)
Indirect: 0 1 1 0 1 1 0 0 | 1 | indirect field(7)  (see Addressing Modes)

Status bits: Does not affect C. Words / Cycles: 1 word; 1 cycle for a single execution with the operand in DARAM.

Cycle class: see Instruction Timing. Example: XORI DAT127 exclusive-ORs the data word with ACCL.

XORK

Toolchain mnemonic for the two-word long-immediate form of XOR.

Syntax: XORK #lk [,shift] Operation: (PC) + 2 -> PC; (ACC(31-0)) XOR (lk << shift) -> ACC(31-0). The constant is shifted left as defined by the shift code and zero-extended on both ends. Operands: lk: 16-bit constant; 0 <= shift <= 16. Opcode:

Shift 0..15: 1 0 1 1 1 1 1 1 1 1 0 1 | SHFT(4)        -> base 0xBFD0 (fmt 0x12)
Shift 16:    1 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1          (0xBE83)
followed by the 16-bit constant

Status bits: Does not affect C. Not affected by SXM. Words / Cycles: 2 words; not repeatable; 2 cycles for a single execution.

Cycle class: see Instruction Timing. Example: XORK #0F0F0h,4 exclusive-ORs the shifted constant with ACC.

XPL

Exclusive-ORs data memory with the DBMR or a long immediate, writing back to data memory.

Syntax: XPL [#lk,] dma (direct); XPL [#lk,] {ind} [,ARn] (indirect) Operation: No long immediate: (PC) + 1 -> PC; (dma) XOR (DBMR) -> dma. Long immediate specified: (PC) + 2 -> PC; (dma) XOR lk -> dma. The accumulator is unaffected in both cases. If the result is 0 the TC bit is set, otherwise it is cleared. Operands: 0 <= dma <= 127; 0 <= n <= 7; lk: 16-bit constant; ind: * *+ *- *0+ *0- *BR0+ *BR0- Opcode:

Direct, no long imm:  0 1 0 1 1 0 0 0 | 0 | dma(7)        (0x5800; see XPLI)
Indirect, no long imm:0 1 0 1 1 0 0 0 | 1 | indirect(7)   (see XPLI)
Direct, long imm:     0 1 0 1 1 1 0 0 | 0 | dma(7)        + 16-bit constant (0x5C00; see XPLK)
Indirect, long imm:   0 1 0 1 1 1 0 0 | 1 | indirect(7)   + 16-bit constant (see XPLK)
toolchain group base: 0x0005 (fmt 0x1e)

Status bits: Affects TC. Words / Cycles: 1 word (no long immediate) or 2 words (long immediate). 1 cycle for a single no-immediate execution with the operand in DARAM; 2 cycles for the long-immediate form.

Cycle class: V (XPL); VI (XPL) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 3[1]	1+p
External	2+2d	2+2d	2+2d	5+2d+p

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	2n-2	2n-2	2n-2, 2n+1[1]	2n-2+p
External	4n-2+2nd	4n-2+2nd	4n-2+2nd	4n+1+2nd+p

[1] If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	2	2	2	2+2p
SARAM	2	2	2	2+2p
External	3+2d	3+2d	3+2d	6+2d+2p

Cycles for a Repeat (RPT) Execution (long immediate specified)

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n+1	n+1	n+1	n+1+2p
SARAM	2n-1	2n-1	2n-1, 2n+2[1]	2n-1+2p
External	4n-1+2nd	4n-1+2nd	4n-1+2nd	4n+2+2nd+2p

[1] If the operand and the code are in the same SARAM block Example: XPL #100h,DAT60 exclusive-ORs 100h into DAT60.

XPLI

Toolchain mnemonic for the single-word (DBMR) form of XPL.

Syntax: XPLI dma (direct); XPLI {ind} [,ARn] (indirect) Operation: (PC) + 1 -> PC; (dma) XOR (DBMR) -> dma. The accumulator is unaffected. TC is set if the result is 0, otherwise cleared. Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: * *+ *- *0+ *0- *BR0+ *BR0- Opcode:

Direct:   0 1 0 1 1 0 0 0 | 0 | dma(7)            -> base 0x5800 (fmt 0x01)
Indirect: 0 1 0 1 1 0 0 0 | 1 | indirect field(7)  (see Addressing Modes)

Status bits: Affects TC. Words / Cycles: 1 word; 1 cycle for a single execution with the operand in DARAM.

Cycle class: see Instruction Timing. Example: XPLI DAT60 exclusive-ORs DAT60 with the DBMR, writing the result back to DAT60.

XPLK

Toolchain mnemonic for the two-word long-immediate form of XPL.

Syntax: XPLK #lk, dma (direct); XPLK #lk, {ind} [,ARn] (indirect) Operation: (PC) + 2 -> PC; (dma) XOR lk -> dma. The accumulator is unaffected. TC is set if the result is 0, otherwise cleared. Operands: 0 <= dma <= 127; 0 <= n <= 7; lk: 16-bit constant; ind: * *+ *- *0+ *0- *BR0+ *BR0- Opcode:

Direct:   0 1 0 1 1 1 0 0 | 0 | dma(7)            -> base 0x5C00 (fmt 0x14)
Indirect: 0 1 0 1 1 1 0 0 | 1 | indirect field(7)
followed by the 16-bit constant

Status bits: Affects TC. Words / Cycles: 2 words; 2 cycles for a single execution with the operand in DARAM.

Cycle class: see Instruction Timing. Example: XPLK #1000h,*,AR6 exclusive-ORs 1000h into the word at the current AR, then points ARP at AR6.

ZAC

Not covered by the provided SPRU056D excerpt (lines 19225-20102).

Syntax: not specified Operation: not specified Operands: not specified Opcode: base 0xB900 (fmt 0x00) from the toolchain table; manual bit-field row not specified. Status bits: not specified Words / Cycles: not specified

Cycle class: see Instruction Timing. Example: not specified

ZALH

Not covered by the provided SPRU056D excerpt (lines 19225-20102).

Syntax: not specified Operation: not specified Operands: not specified Opcode: base 0x6A00 (fmt 0x01) from the toolchain table; manual bit-field row not specified. Status bits: not specified Words / Cycles: not specified

Cycle class: see Instruction Timing. Example: not specified

ZALR

Loads data memory into ACCH with rounding.

Syntax: ZALR dma (direct); ZALR {ind} [,ARn] (indirect) Operation: (PC) + 1 -> PC; 8000h -> ACC(15-0); (dma) -> ACC(31-16). The value is rounded by adding 1/2 LSB: bits 0-14 of ACCL are cleared and ACCL bit 15 is set. Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: * *+ *- *0+ *0- *BR0+ *BR0- Opcode:

Direct:   0 1 1 0 1 0 0 0 | 0 | dma(7)            -> base 0x6800 (fmt 0x01)
Indirect: 0 1 1 0 1 0 0 0 | 1 | indirect field(7)  (see Addressing Modes)

Status bits: Does not affect C. Words / Cycles: 1 word; 1 cycle for a single execution with the operand in DARAM.

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Operand	ROM	DARAM	SARAM	External Memory
DARAM	1	1	1	1+p
SARAM	1	1	1, 2[1]	1+p
External	1+d	1+d	1+d	2+d+p

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

Operand	ROM	DARAM	SARAM	External Memory
DARAM	n	n	n	n+p
SARAM	n	n	n, n+1[1]	n+p
External	n+nd	n+nd	n+nd	n+1+p+nd

[1] If the operand and the code are in the same SARAM block Example: ZALR DAT3 loads DAT3 into ACCH and sets ACCL to 8000h.

ZALS

Not covered by the provided SPRU056D excerpt (lines 19225-20102).

Syntax: not specified Operation: not specified Operands: not specified Opcode: base 0x6900 (fmt 0x01) from the toolchain table; manual bit-field row not specified. Status bits: not specified Words / Cycles: not specified

Cycle class: see Instruction Timing. Example: not specified

ZAP

Clears the accumulator and the product register.

Syntax: ZAP Operation: (PC) + 1 -> PC; 0 -> ACC; 0 -> PREG. Speeds up preparation for a repeated multiply/accumulate. Operands: None. Opcode:

1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1   -> base 0xBE59 (fmt 0x00)

Status bits: None affected. Words / Cycles: 1 word; 1 cycle for a single execution.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p
Example: `ZAP` clears both ACC and PREG to 0.

ZPR

Clears the product register.

Syntax: ZPR Operation: (PC) + 1 -> PC; 0 -> PREG. Operands: None. Opcode:

1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 0   -> base 0xBE58 (fmt 0x00)

Status bits: None affected. Words / Cycles: 1 word; 1 cycle for a single execution.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

ROM	DARAM	SARAM	External Memory
1	1	1	1+p

Cycles for a Repeat (RPT) Execution

ROM	DARAM	SARAM	External Memory
n	n	n	n+p
Example: `ZPR` clears PREG to 0.

License

c5xtools wiki

Start here

The TMS320C5x processor

Writing assembly

The instruction set

A: ABS ADCB ADD ADDB ADDC ADDH ADDI ADDK ADDS ADDT ADLK ADRK AND ANDB ANDI ANDK APAC APL APLI APLK

B: B BACC BACCD BANZ BANZD BBNZ BBZ BC BCND BCNDD BD BDDD BDSD BGEZ BGZ BIOZ BIT BITT BKDK BLDD BLDP BLEZ BLKD BLKP BLPD BLZ BNC BNV BNZ BPSD BSAR BV BZ

C: CALA CALAD CALL CALLD CC CCD CLRC CMPL CMPR CNFD CNFP CONF CPL CPLI CPLK CRGT CRLT

D: DINT DMOV

E: EHWBS EHWBT EINT EMPSD EMRET ESTOP ESTPD ETRAP EXAR

F: FORT

I: IDLE IDLE1 IDLE2 IN INTR

L: LAC LACB LACC LACI LACK LACL LACT LALK LAMM LAR LARK LARP LDP LDPI LDPK LMMR LPH LRLK LST LST0 LST1 LT LTA LTD LTP LTS

M: MAC MACD MADD MADS MAR MPY MPYA MPYI MPYK MPYS MPYU MRKL

N: NEG NMI NOP NORM

O: OPL OPLI OPLK OR ORB ORI ORK OUT

P: PAC POP POPD PSHD PUSH

R: RC RET RETC RETCD RETD RETE RETI RFSM RHM ROL ROLB ROR RORB ROVM RPT RPTB RPTI RPTK RPTR RPTZ RSXM RTC RTXM RXF

S: SACB SACH SACL SAMM SAR SATH SATL SBB SBBB SBLK SBRK SC SETC SFL SFLB SFR SFRB SFSM SHM SMMR SOVM SPAC SPH SPL SPLK SPM SQRA SQRS SST SST0 SST1 SSXM STC STXM SUB SUBB SUBC SUBH SUBI SUBK SUBS SUBT SWI SXF

T: TBLR TBLW TRAP TRAPD

X: XC XOR XORB XORI XORK XPL XPLI XPLK

Z: ZAC ZALH ZALR ZALS ZAP ZPR

Building a program

The tools

c5xtools vs the TI toolchain

Normative sources: TI SPRU056D and SPRU018D (see References).

Changelog