Instruction Timing

Normative source: SPRU056D, Appendix B (Instruction Classes and Cycles), with the cycle notation from chapter 6. Cycle counts are machine cycles (CLKOUT1 periods) for a single execution; repeats and wait states add to them as described below.

Notation

Where the instruction executes (the code source):

Source	Meaning
ROM	on-chip program ROM
DARAM	on-chip dual-access program RAM
SARAM	on-chip single-access program RAM
External	external program memory

Where an operand lives:

Operand	Meaning
DARAM	internal dual-access RAM
SARAM	internal single-access RAM
External	external memory
ROM	internal program ROM
MMR	memory-mapped register
MMPORT	memory-mapped I/O port

Wait-state and repeat variables (with optional src, dst, code subscripts):

Symbol	Meaning
d	data-memory wait states for an external data access
io	I/O wait states for an external I/O access
p	program-memory wait states for an external program access
n	repetitions (n > 2 to fill the pipeline) of a repeated instruction

An external read takes at least one machine cycle; an external write at least two (three if it is immediately next to an external read). With m on-chip wait states both reads and writes take m+1 cycles.

Cycle classes

Every instruction falls into one of these classes (SPRU056D Table B-1).

Class	Words, cycles and access pattern
I	1 word, 1 cycle, no memory operands
IIA	1 word, 1 cycle, memory read operand
IIB	1 word, 1 cycle, memory-mapped register read
III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
IVA	1 word, 1 cycle, memory write operand
IVB	1 word, 1 cycle, memory-mapped register write
V	1 word, 1 cycle, memory read and write
VI	2 words, 2 cycles, memory read and write
VIIa	2 words, 2 cycles, memory read operand
VIIb	2 words, 2 cycles, memory write operand, not repeatable
VIII	2 words, 4 cycles, program-counter discontinuity, no delayed slots, not repeatable
IX	2 words, 2 cycles, program-counter discontinuity, 2 delayed slots, not repeatable
X	1 word, 4 cycles, program-counter discontinuity, no delayed slots, not repeatable
XI	1 word, 2 cycles, program-counter discontinuity, 2 delayed slots, not repeatable
XII	2 words, 3 cycles, block data transfer, data to data space
XIII	1 word, 2 cycles, block data transfer, data to data space
XIV	2 words, 3 cycles, block data transfer, program to data space
XV	1 word, 2 cycles, block data transfer, program to data space
XVI	1 word, 2 cycles, block data transfer, data to program space
XVII	1 word, 3 cycles, table read
XVIII	1 word, 3 cycles, table write
XIX	2 words, 3 cycles, multiply accumulate
XX	1 word, 2 cycles, multiply accumulate
XXI	2 words, 3 cycles, multiply accumulate with data move
XXII	1 word, 2 cycles, multiply accumulate with data move
XXIII	2 words, 2 cycles, memory-mapped register load
XXIV	2 words, 2 cycles, memory-mapped register store
XXV	2 words, 3 cycles, output port
XXVI	2 words, 2 cycles, input port
XXVII	1 word, 2 cycles, pipeline-protected, memory read
XXVIII	1 word, 2 cycles, pipeline-protected, memory read, not repeatable
XXIIX	1 word, 2 cycles, no memory access, not repeatable, pipeline protected

Instruction to cycle class

From SPRU056D Table B-2. A mnemonic with several forms appears once per form, since the form determines the class.

Instruction form	Cycle class	Words, cycles, access
`ABS`	I	1 word, 1 cycle, no memory operands
`ADCB`	I	1 word, 1 cycle, no memory operands
`ADD`	IIA	1 word, 1 cycle, memory read operand
`ADD #k`	I	1 word, 1 cycle, no memory operands, not repeatable
`ADD #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`ADDB`	I	1 word, 1 cycle, no memory operands
`ADDC`	IIA	1 word, 1 cycle, memory read operand
`ADDS`	IIA	1 word, 1 cycle, memory read operand
`ADDT`	IIA	1 word, 1 cycle, memory read operand
`ADRK #k`	I	1 word, 1 cycle, no memory operands, not repeatable
`AND`	IIA	1 word, 1 cycle, memory read operand
`AND #lk`	III	2 words, 2 cycles long-immediate operand, no memory access, not repeatable
`ANDB`	I	1 word, 1 cycle, no memory operands
`APAC`	I	1 word, 1 cycle, no memory operands
`APL`	V	1 word, 1 cycle, memory read and write
`APL`	VI	2 words, 2 cycles, memory read and write
`B`	VIII	2 words, 4 cycles program counter discontinuity, no delayed slots, not repeatable
`BACC`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`BACCD`	XI	1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable Instruction Classes and Cycles B-5
`BANZ`	VIII	2 words, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`BANZD`	IX	2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable
`BCND`	VIII	2 words, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`BCNDD`	IX	2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable
`BD`	IX	2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable
`BIT`	IIA	1 word, 1 cycle, memory read operand
`BITT`	IIA	1 word, 1 cycle, memory read operand
`BLDD`	XIII	1 word, 2 cycles, block data transfer, data to data space
`BLDD`	XII	2 words, 3 cycles, block data transfer, data to data space
`BLDP`	XVI	1 word, 2 cycles, block data transfer, data to program space
`BLPD`	XV	1 word, 2 cycles, block data transfer, program to data space
`BLPD`	XIV	2 words, 3 cycles, block data transfer, program to data space
`BSAR`	I	1 word, 1 cycle, no memory operands
`CALA`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`CALAD`	XI	1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable
`CALL`	VIII	2 words, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`CALLD`	IX	2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable
`CC`	VIII	2 words, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`CCD`	IX	2 words, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable
`CLRC`	I	1 word, 1 cycle, no memory operands
`CMPL`	I	1 word, 1 cycle, no memory operands
`CMPR`	I	1 word, 1 cycle, no memory operands
`CPL`	IIA	1 word, 1 cycle, memory read operand
`CPL #lk`	VIIa	2 words, 2 cycles, memory read operand
`CRGT`	I	1 word, 1 cycle, no memory operands
`CRLT`	I	1 word, 1 cycle, no memory operands
`DMOV`	V	1 word, 1 cycle, memory read and write
`EXAR`	I	1 word, 1 cycle, no memory operands
`IDLE`	I	1 word, 1 cycle, no memory operands, not repeatable
`IDLE2`	I	1 word, 1 cycle, no memory operands, not repeatable
`IN`	XXVI	2 words, 2 cycles, input port
`INTR`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`LACB`	I	1 word, 1 cycle, no memory operands
`LACC`	IIA	1 word, 1 cycle, memory read operand
`LACC #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`LACL`	IIA	1 word, 1 cycle, memory read operand
`LACL #k`	I	1 word, 1 cycle, no memory operands, not repeatable
`LACT`	IIA	1 word, 1 cycle, memory read operand
`LAMM`	IIB	1 word, 1 cycle, memory-mapped register read
`LAR`	XXVII	1 word, 2 cycles, pipeline-protected, memory read
`LAR ARn, #k`	XXVIII	1 word, 2 cycles, pipeline-protected, memory read, not repeatable Instruction Classes and Cycles B-7
`LAR ARn, #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`LDP`	XXVII	1 word, 2 cycles, pipeline-protected, memory read
`LDP #k`	XXVIII	1 word, 2 cycles, pipeline-protected, memory read, not repeatable
`LMMR`	XXIII	2 words, 2 cycles, memory-mapped register load
`LPH`	IIA	1 word, 1 cycle, memory read operand
`LST`	XXVII	1 word, 2 cycles, pipeline-protected, memory read
`LT`	IIA	1 word, 1 cycle, memory read operand
`LTA`	IIA	1 word, 1 cycle, memory read operand
`LTD`	V	1 word, 1 cycle, memory read and write
`LTP`	IIA	1 word, 1 cycle, memory read operand
`LTS`	IIA	1 word, 1 cycle, memory read operand
`MAC`	XIX	2 words, 3 cycles, multiply accumulate
`MACD`	XXI	2 words, 3 cycles, multiply accumulate with data move
`MADD`	XXII	1 word, 2 cycles, multiply accumulate with data move
`MADS`	XX	1 word, 2 cycles, multiply accumulate
`MAR`	I	1 word, 1 cycle, no memory operands
`MPY`	IIA	1 word, 1 cycle, memory read operand
`MPY #k`	I	1 word, 1 cycle, no memory operands, not repeatable
`MPY #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`MPYA`	IIA	1 word, 1 cycle, memory read operand
`MPYS`	IIA	1 word, 1 cycle, memory read operand
`MPYU`	IIA	1 word, 1 cycle, memory read operand
`NEG`	I	1 word, 1 cycle, no memory operands
`NMI`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`NOP`	I	1 word, 1 cycle, no memory operands
`NORM`	I	1 word, 1 cycle, no memory operands
`OPL`	V	1 word, 1 cycle, memory read and write
`OPL`	VI	2 words, 2 cycles, memory read and write
`OR`	IIA	1 word, 1 cycle, memory read operand
`OR #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`ORB`	I	1 word, 1 cycle, no memory operands
`OUT`	XXV	2 words, 3 cycles, output port
`PAC`	I	1 word, 1 cycle, no memory operands
`POP`	I	1 word, 1 cycle, no memory operands
`POPD`	IVA	1 word, 1 cycle, memory write operand
`PSHD`	IIA	1 word, 1 cycle, memory read operand
`PUSH`	I	1 word, 1 cycle, no memory operands
`RET`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`RETC`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`RETCD`	XI	1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable
`RETD`	XI	1 word, 2 cycles, program counter discontinuity, 2 delayed slots, not repeatable
`RETE`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`RETI`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`ROL`	I	1 word, 1 cycle, no memory operands Instruction Classes and Cycles B-9
`ROLB`	I	1 word, 1 cycle, no memory operands
`ROR`	I	1 word, 1 cycle, no memory operands
`RORB`	I	1 word, 1 cycle, no memory operands
`RPT`	IIA	1 word, 1 cycle, memory read operand, not repeatable
`RPT #k`	XXIX	1 word, 2 cycle, no memory operands, not repeatable
`RPT #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`RPTB`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`RPTZ #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`SACB`	I	1 word, 1 cycle, no memory operands
`SACH`	IVA	1 word, 1 cycle, memory write operand
`SACL`	IVA	1 word, 1 cycle, memory write operand
`SAMM`	IVB	1 word, 1 cycle, memory-mapped register write
`SAR`	IVA	1 word, 1 cycle, memory write operand
`SATH`	I	1 word, 1 cycle, no memory operands
`SATL`	I	1 word, 1 cycle, no memory operands
`SBB`	I	1 word, 1 cycle, no memory operands
`SBBB`	I	1 word, 1 cycle, no memory operands
`SBRK #k`	I	1 word, 1 cycle, no memory operands, not repeatable
`SETC`	I	1 word, 1 cycle, no memory operands
`SFL`	I	1 word, 1 cycle, no memory operands
`SFLB`	I	1 word, 1 cycle, no memory operands
`SFR`	I	1 word, 1 cycle, no memory operands
`SFRB`	I	1 word, 1 cycle, no memory operands
`SMMR`	XXIV	2 words, 2 cycles, memory-mapped register store
`SPAC`	I	1 word, 1 cycle, no memory operands
`SPH`	IVA	1 word, 1 cycle, memory write operand
`SPL`	IVA	1 word, 1 cycle, memory write operand
`SPLK`	VIIb	2 words, 2 cycles, memory write operand, not repeatable
`SPM`	I	1 word, 1 cycle, no memory operands, not repeatable
`SQRA`	IIA	1 word, 1 cycle, memory read operand
`SQRS`	IIA	1 word, 1 cycle, memory read operand
`SST`	IVA	1 word, 1 cycle, memory write operand
`SUB`	IIA	1 word, 1 cycle, memory read operand
`SUB #k`	I	1 word, 1 cycle, no memory operands, not repeatable
`SUB #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`SUBB`	IIA	1 word, 1 cycle, memory read operand
`SUBC`	IIA	1 word, 1 cycle, memory read operand
`SUBS`	IIA	1 word, 1 cycle, memory read operand
`SUBT`	IIA	1 word, 1 cycle, memory read operand
`TBLR`	XVII	1 word, 3 cycles, table read
`TBLW`	XVIII	1 word, 3 cycles, table write
`TRAP`	X	1 word, 4 cycles, program counter discontinuity, no delayed slots, not repeatable
`XC`	I	1 word, 1 cycle, no memory operands, not repeatable
`XOR`	IIA	1 word, 1 cycle, memory read operand
`XOR #lk`	III	2 words, 2 cycles, long-immediate operand, no memory access, not repeatable
`XORB`	I	1 word, 1 cycle, no memory operands
`XPL`	V	1 word, 1 cycle, memory read and write
`XPL`	VI	2 words, 2 cycles, memory read and write Instruction Classes and Cycles B-11
`ZALR`	IIA	1 word, 1 cycle, memory read operand
`ZAP`	I	1 word, 1 cycle, no memory operands
`ZPR`	I	1 word, 1 cycle, no memory operands Appendix AppendixCA