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How to interpret Interfaces of the Standard Library
Chisel contains a Standard Library of Interfaces:
DecoupledIO- a Bundle with a ready-valid interface
ValidIO- a Bundle with a valid interface
Queue- a Module providing a hardware Queue
Pipe- a Module delaying input data
Arbiter- a Module connecting multiple producers to one consumer
How are these interpreted in hardware? What do they synthesize to?
A full answer is still to be provided, but for now all the knowledge on this matter is collected within this StackOverflow question.
Please feel free to contribute, either here directly or by answering the mentioned question.