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synaptic-wiring is the connectivity and temporal delay infrastructure layer for Spiking Neural Networks (SNNs). It answers the questions of which neuron connects to which, how strongly, and how long the spike takes to arrive. The crate provides deterministic topology generators, axonal delay management via high-performance ring buffers, biological constraints such as Dale's law, and compressed sparse row (CSR) weight matrices suitable for CPU or GPU evaluation.
The crate explicitly excludes neuron integration models (such as LIF or Izhikevich) and learning rules, leaving those concerns to the consuming application or dedicated neuron-model crates README.md:15-46, src/lib.rs:3-64.
The codebase is organized into several focused modules handling topology, temporal queuing, orchestration, sparse storage, routing, and error definitions.
graph TD
subgraph NaturalLanguageSpace ["Natural Language Space"]
TopologyGen["Topology Generators"]
DelayBuf["Axonal Delay Queue"]
Orchestrator["Mesh Orchestrator"]
SparseMap["Sparse Weight Storage"]
Classifier["Channel Classifier"]
end
subgraph CodeEntitySpace ["Code Entity Space"]
topology["topology module"] --> SynapticGraph["SynapticGraph"]
delay["delay module"] --> SpikeDelayBuffer["SpikeDelayBuffer"]
mesh["mesh module"] --> SynapticMesh["SynapticMesh"]
sparse["sparse module"] --> SparseSynapticMap["SparseSynapticMap"]
router["router module"] --> ChannelRouter["ChannelRouter"]
error["error module"] --> MeshError["MeshError"]
types["types module"] --> SynapseDescriptor["SynapseDescriptor"]
end
TopologyGen -.-> topology
DelayBuf -.-> delay
Orchestrator -.-> mesh
SparseMap -.-> sparse
Classifier -.-> router
Sources: src/lib.rs:43-151, README.md:48-56
This parent page provides a high-level overview of the library. For implementation specifics, tutorials, and historical versioning data, refer to the following child pages:
This child page covers installation procedures, the Minimum Supported Rust Version (MSRV), a minimal propagate loop example, and the full set of re-exported types provided at the crate root in src/lib.rs. It provides the foundational guide for integrating synaptic-wiring into an external SNN simulation loop.
For details, see Getting Started & Public API.
Sources: README.md:69-115, src/lib.rs:146-180
This child page details the evolution of the crate through its CHANGELOG.md, documenting the crate rename from synaptic-mesh to synaptic-wiring, breaking API changes across versions, and the CI release automation workflows that govern registry publication and Linear issue synchronization.
For details, see Release History and Versioning.
Sources: CHANGELOG.md:1-86, README.md:21-25
- 1. Overview
- 1.1. Getting Started & Public API
- 1.2. Release History and Versioning
- 2. Core Runtime: SynapticMesh
- 2.1. Propagation APIs and Tick Semantics
- 2.2. Spike Delay Buffer (Ring Buffer)
- 2.3. Core Types and Error Model
- 2.4. Checkpointing and Serde State Restoration
- 3. Topology Subsystem
- 3.1. SynapticGraph and CSR Representation
- 3.2. Topology Generators
- 3.3. Wiring Rules, Dale's Law and Delay Assignment
- 3.4. Topology Digest
- 4. Sparse Maps and Channel Routing
- 4.1. ChannelRouter and RouterConfig
- 4.2. Neuromodulation and Plasticity
- 4.3. SparseSynapticMap (CSR)
- 5. Testing, Benchmarks and Quality Gates
- 5.1. Propagation Contract Tests
- 5.2. Checkpoint Resume Property Suite
- 5.3. Benchmarks and Unit Test Module
- 6. Build, CI and Project Tooling
- 6.1. Cargo Manifest, Profiles and Dependencies
- 6.2. CI Workflows and Packaging Validation
- 6.3. Code Quality, Licensing and Review Gates
- 7. Glossary