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1.1 Getting Started Public API
Relevant source files
The following files were used as context for generating this wiki page:
This page covers the initial setup, Minimum Supported Rust Version (MSRV), public API re-exports, and a minimal execution loop for synaptic-wiring. It serves as the entry point for integrating the connectivity and temporal delay layer into spiking neural network (SNN) simulations.
Sources: Cargo.toml:1-16](), [src/lib.rs:3-13
synaptic-wiring is distributed via crates.io. The package requires Rust edition 2024 and enforces a strict Minimum Supported Rust Version (MSRV).
Add the dependency to your Cargo.toml:
[dependencies]
synaptic-wiring = "0.3.0"The crate maintains a pre-1.0 experimental API where minor releases may introduce breaking changes. For precise builds, pin the exact version (= "0.3.0").
-
MSRV: Rust
1.98.1(configured viarust-versioninCargo.toml). -
Edition:
2024 -
Runtime Dependencies:
serde(withderivefeature) andsha2. -
Dev Dependencies:
serde_json,postcard(for binary checkpointing), andcriterion(for benchmarks).
[package]
name = "synaptic-wiring"
version = "0.3.0"
edition = "2024"
rust-version = "1.98.1"
license = "MIT OR Apache-2.0"
[dependencies]
serde = { version = "1.0", features = ["derive"] }
sha2 = "0.10"Sources: `Cargo.toml:1-46
The crate root (src/lib.rs) exposes core orchestrators, temporal buffers, and error models while organizing internal subsystems into distinct modules.
| Module Path | Primary Responsibility |
|---|---|
synaptic_wiring::mesh |
Owns [SynapticMesh], the orchestrator managing topology and axonal delays. |
synaptic_wiring::delay |
Owns [SpikeDelayBuffer], a ring-buffer queue for tick-aligned spike propagation. |
synaptic_wiring::topology |
Network graph construction, CSR layout, generators, and [TopologyDigest]. |
synaptic_wiring::sparse |
Compressed Sparse Row (CSR) synaptic maps for GPU-optimized weight storage. |
synaptic_wiring::router |
Optional multi-channel classifier using [NeuromodNeuron]. |
synaptic_wiring::error |
Defines [MeshError] and [Result] types. |
synaptic_wiring::types |
Descriptors (SynapseDescriptor), indices, and configuration types. |
Sources: `src/lib.rs:136-151
graph TD
lib["src/lib.rs"] --> meshMod["synaptic_wiring::mesh"]
lib --> delayMod["synaptic_wiring::delay"]
lib --> topoMod["synaptic_wiring::topology"]
lib --> sparseMod["synaptic_wiring::sparse"]
lib --> routerMod["synaptic_wiring::router"]
lib --> errMod["synaptic_wiring::error"]
lib --> typesMod["synaptic_wiring::types"]
meshMod --> SynapticMesh["SynapticMesh"]
delayMod --> SpikeDelayBuffer["SpikeDelayBuffer"]
errMod --> MeshError["MeshError"]
errMod --> ResultType["Result"]
classDef default fill:none,stroke:#000,stroke-width:1px;
Figure 1: Public module structure and re-exported types.
Sources: `src/lib.rs:136-151
The following example demonstrates how to construct a small-world network topology, wrap it in a [SynapticMesh] instance, and execute a propagation loop where source spikes are converted into delayed synaptic currents.
use synaptic_wiring::topology::generate_small_world;
use synaptic_wiring::mesh::SynapticMesh;
fn main() -> synaptic_wiring::Result<()> {
// 1. Build a 256-neuron small-world network with delays up to 5 ticks
// Parameters: N=256, k=6 neighbors, beta=0.2 rewiring, max_delay=5, inh_fraction=0.2
let graph = generate_small_world(256, 6, 0.2, 5, 0.2)?;
// 2. Wrap the graph in the SynapticMesh orchestrator
let mut mesh = SynapticMesh::new(graph);
// 3. Simulation tick: provide boolean spike vector -> receive f32 currents
let mut spikes = vec![false; 256];
spikes[0] = true; // Neuron 0 fires
let currents = mesh.propagate(&spikes)?;
// currents[i] represents the total incoming synaptic current at neuron i for this tick
Ok(())
}Sources: README.md:97-115](), [src/lib.rs:67-81
SynapticMesh::propagate() executes a single simulation hop. It translates input spikes into currents arriving at target neurons on the current tick, accounting for pre-configured axonal propagation delays stored in the ring buffer.
sequenceDiagram
autonumber
participant User as "User Simulation Loop"
participant Mesh as "SynapticMesh"
participant Buffer as "SpikeDelayBuffer"
participant Graph as "SynapticGraph"
User->>Mesh: "propagate(&spikes)"
Mesh->>Buffer: "inject(spikes) & advance()"
Buffer->>Graph: "Lookup delayed edges (CSR)"
Graph-->>Buffer: "Target currents & weights"
Buffer-->>Mesh: "Vec<f32> currents"
Mesh-->>User: "Return tick currents"
Figure 2: Data flow during a single propagation tick.
- 1. Overview
- 1.1. Getting Started & Public API
- 1.2. Release History and Versioning
- 2. Core Runtime: SynapticMesh
- 2.1. Propagation APIs and Tick Semantics
- 2.2. Spike Delay Buffer (Ring Buffer)
- 2.3. Core Types and Error Model
- 2.4. Checkpointing and Serde State Restoration
- 3. Topology Subsystem
- 3.1. SynapticGraph and CSR Representation
- 3.2. Topology Generators
- 3.3. Wiring Rules, Dale's Law and Delay Assignment
- 3.4. Topology Digest
- 4. Sparse Maps and Channel Routing
- 4.1. ChannelRouter and RouterConfig
- 4.2. Neuromodulation and Plasticity
- 4.3. SparseSynapticMap (CSR)
- 5. Testing, Benchmarks and Quality Gates
- 5.1. Propagation Contract Tests
- 5.2. Checkpoint Resume Property Suite
- 5.3. Benchmarks and Unit Test Module
- 6. Build, CI and Project Tooling
- 6.1. Cargo Manifest, Profiles and Dependencies
- 6.2. CI Workflows and Packaging Validation
- 6.3. Code Quality, Licensing and Review Gates
- 7. Glossary