3 Topology Subsystem

Topology Subsystem

Relevant source files

The following files were used as context for generating this wiki page:

• src/topology/digest.rs
• src/topology/mod.rs
• tests/topology_digest.rs

The Topology Subsystem is responsible for constructing, validating, and representing the structural graph of spiking neural networks within synaptic-wiring. It provides the Compressed Sparse Row (CSR) adjacency structure [SynapticGraph], deterministic graph generators for classic network science models, rule-based wiring and polarity enforcement (such as Dale's Law), and versioned canonical hashing via [TopologyDigest].

Sources: [src/topology/mod.rs:1-22]()

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3.1 SynapticGraph and CSR Representation

The graph structure underlying the runtime mesh is represented in Compressed Sparse Row (CSR) format via SynapticGraph. This layout optimizes memory locality and traversal performance during spike propagation ticks. The representation builds directly from collections of SynapseDescriptor structs, enforcing neuron count bounds and validating edge integrity before exporting flat arrays suitable for host-device execution or zero-allocation runtime routing.

For details, see SynapticGraph and CSR Representation.

graph TD
    A["SynapticDescriptorCollection"] -->| "SynapticGraph::from_descriptors" | B["SynapticGraph"]
    B -->| "CSR Layout" | C["RowOffsets_CSR"]
    B -->| "CSR Layout" | D["ColIndices_CSR"]
    B -->| "CSR Layout" | E["Weights_And_Delays"]
    B -->| "Export" | F["GPUArrayExport"]

    subgraph "Code Entity Space"
        B
        C
        D
        E
        F
    end

    subgraph "Natural Language Space"
        A
    end

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Sources: [src/topology/mod.rs:11](), [src/topology/digest.rs:86-92]()

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3.2 Topology Generators

The subsystem includes a suite of deterministic topology generators that instantiate complex network structures. Supported models include small-world networks (generate_small_world), scale-free networks (generate_scale_free), Erdős-Rényi random graphs (generate_random), and multi-layered feedforward/recurrent architectures (generate_layered). These generators rely on golden-ratio deterministic hashing to ensure reproducible connectivity regardless of thread concurrency or execution platform.

For details, see Topology Generators.

graph TD
    A["GeneratorParameters"] -->| "generate_small_world" | B["SynapticGraph"]
    A -->| "generate_scale_free" | B
    A -->| "generate_random" | B
    A -->| "generate_layered" | B

    subgraph "Code Entity Space"
        B
        A
    end

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Sources: [src/topology/mod.rs:10](), [src/topology/mod.rs:18-20]()

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3.3 Wiring Rules, Dale's Law and Delay Assignment

Wiring rules govern how neurons establish synaptic connections and how physiological constraints are applied. The module wiring_rules.rs supplies utilities such as apply_dale_polarity—which enforces Dale's Principle (neurons maintain a uniform excitatory or inhibitory neurotransmitter phenotype across all outgoing synapses)—and assign_delays, which allocates axonal propagation delays within configured minimum and maximum tick bounds.

For details, see Wiring Rules, Dale's Law and Delay Assignment.

graph TD
    A["UnprocessedGraph"] -->| "apply_dale_polarity" | B["PolarityEnforcedGraph"]
    B -->| "assign_delays" | C["FullyWiredGraph"]

    subgraph "Code Entity Space"
        A
        B
        C
    end

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Sources: [src/topology/mod.rs:12](), [src/topology/mod.rs:22]()

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3.4 Topology Digest

To support checkpoints, experiment replay, and cross-runtime verification, the subsystem implements a versioned SHA-256 canonical digest scheme via [TopologyDigest]. The digest calculates a deterministic hash over the logical graph structure, independent of CSR insertion order, map iteration variance, host endianness, or serialization formatting.

For details, see Topology Digest.

graph TD
    A["SynapticGraph"] -->| "TopologyDigest::from_graph" | B["canonical_edges"]
    B -->| "Sort & Encode" | C["HashPreprint_V1"]
    C -->| "Sha256::digest" | D["TopologyDigest"]

    subgraph "Code Entity Space"
        A
        B
        C
        D
    end

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Sources: [src/topology/digest.rs:78-92], [tests/topology_digest.rs:56-71]