2 Core Runtime SynapticMesh

Core Runtime: SynapticMesh

Relevant source files

The following files were used as context for generating this wiki page:

• src/mesh.rs

Purpose and Scope

The SynapticMesh is the primary top-level orchestrator of the synaptic-wiring codebase, defined in [src/mesh.rs:37-63](). It bridges structural network topology with temporal delay mechanics, converting instantaneous source spikes into time-delayed synaptic currents over discrete simulation ticks.

This page serves as a high-level parent guide to the core runtime subsystem. Detailed technical breakdowns, API contracts, ring buffer mechanics, error handling, and serialization are documented in the respective child sections below.

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Architecture Overview

The runtime coordinates three principal components: the SynapticMesh orchestrator itself, the SynapticGraph topology container, and the SpikeDelayBuffer ring buffer.

graph TD
    SM["SynapticMesh"] --> SG["SynapticGraph"]
    SM --> SDB["SpikeDelayBuffer"]
    SM --> T["TickCounter"]
    
    subgraph Code_Entities
        SM["SynapticMesh (src/mesh.rs)"]
        SG["SynapticGraph (src/topology/graph.rs)"]
        SDB["SpikeDelayBuffer (src/delay.rs)"]
    end

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Sources: src/mesh.rs:37-63, src/topology/graph.rs:1-50, src/delay.rs:1-50

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2.1 Propagation APIs and Tick Semantics

The core execution path is driven by propagate, propagate_into, and graded variant methods that advance the network simulation by a single tick [src/mesh.rs:174-200]. These APIs support zero-allocation execution paths for fixed-rate simulation loops by allowing callers to reuse pre-allocated output buffers.

For full details on return contracts, zero-allocation requirements, and error atomicity, see Propagation APIs and Tick Semantics.

Sources: src/mesh.rs:174-200

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2.2 Spike Delay Buffer (Ring Buffer)

Temporal axonal delays are managed via a dedicated ring buffer implementation located in [src/delay.rs](). This component handles the injection of incoming spikes, advancement of the ring pointer per tick, and the draining of delayed spikes ready for synaptic integration. It enforces strict capacity and max_delay validation rules.

For full details on the buffer design, inject/drain algorithms, and capacity bounds, see Spike Delay Buffer (Ring Buffer).

Sources: src/delay.rs:1-100

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2.3 Core Types and Error Model

Underpinning the runtime are fundamental descriptors and type definitions located in [src/types.rs]() and [src/error.rs](). These include identifiers like NeuronId, Polarity, DelayTicks, structural SynapseDescriptor configurations, and the unified MeshError enumeration governing fallible operations.

For full details on descriptor fields, type constraints, and error variants, see Core Types and Error Model.

Sources: src/types.rs:1-50, src/error.rs:1-50

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2.4 Checkpointing and Serde State Restoration

SynapticMesh implements serde::Serialize and serde::Deserialize via proxy structures to support deterministic checkpointing and state restoration [src/mesh.rs:30-116]. Deserialization routines perform strict invariant validation, ensuring that neuron counts match, buffer capacities satisfy maximum delays, and simulation timestamps are synchronized.

For full details on proxy layouts, deserialization validation, and JSON/postcard formats, see Checkpointing and Serde State Restoration.

Sources: src/mesh.rs:30-116

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Subsystem Collaboration Flow

sequenceDiagram
    participant Caller as "Caller"
    participant Mesh as "SynapticMesh"
    participant Buffer as "SpikeDelayBuffer"
    participant Graph as "SynapticGraph"

    Caller->>Mesh: "propagate(spikes)"
    Mesh->>Buffer: "advance_and_drain()"
    Buffer-->>Mesh: "active_spikes"
    Mesh->>Graph: "csr_matrix_multiplication()"
    Graph-->>Mesh: "synaptic_currents"
    Mesh->>Buffer: "inject(new_spikes)"
    Mesh-->>Caller: "currents_vector"

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Sources: src/mesh.rs:174-250, src/delay.rs:50-150, src/topology/graph.rs:50-120