7 Glossary

Glossary

Relevant source files

The following files were used as context for generating this wiki page:

• README.md
• src/lib.rs
• src/router.rs
• src/topology/graph.rs
• src/types.rs

Purpose and Scope

This page provides formal technical definitions and implementation pointers for domain-specific concepts, architectural patterns, and structural invariants used across synaptic-wiring. Each entry details the theoretical background, how it maps to code entities, and where validation rules or core logic reside in the repository.

Sources: README.md:15-43, src/lib.rs:3-13

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1. Dale's Law (Polarity)

Definition

Dale's law (or Dale's principle) states that a neuron emits the same functional type of neurotransmitter at all of its outgoing synapses. In computational spiking neural networks, this means a neuron is strictly either excitatory (depolarizing, positive sign) or inhibitory (hyperpolarizing, negative sign).

Code Entities and Enforcement

The crate models this via the Polarity enum src/types.rs:29-36 and enforces it during graph construction and CSR validation src/topology/graph.rs:151-160. The effective signed weight combines a non-negative magnitude with the polarity sign multiplier src/types.rs:38-46, src/types.rs:79-87.

graph TD
    subcode["Natural Language & Code Entity Mapping"]
    NL_Dale[""Dale's Law (Excitatory/Inhibitory Split)"" --> ENUM_Pol[""Polarity enum""]
    ENUM_Pol -->|Excitatory| SIGN_Exc[""Polarity::Excitatory (+1.0)""]
    ENUM_Pol -->|Inhibitory| SIGN_Inh[""Polarity::Inhibitory (-1.0)""]
    SIGN_Exc --> DESC[""SynapseDescriptor::effective_weight()""]
    SIGN_Inh --> DESC

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Sources: README.md:36-37, src/types.rs:22-87, src/topology/graph.rs:151-160

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2. CSR (Compressed Sparse Row) Representation

Definition

Compressed Sparse Row (CSR) is a sparse matrix format that stores a matrix as three contiguous vectors: row pointers (row_ptr), column indices (targets), and non-zero values (weights). In synaptic-wiring, this representation is extended with parallel vectors for axonal delays and polarities to form a memory-efficient network topology graph.

Code Entities and Layout

The CSR representation is implemented in SynapticGraph src/topology/graph.rs:32-47 and SparseSynapticMap src/lib.rs:50-50. Deserialization routines rigorously validate index bounds, monotonic row offsets, and weight-polarity agreements src/topology/graph.rs:65-89.

graph TD
    subcode["CSR Data Structure Layout"]
    CSR_Graph[""SynapticGraph"" -->|Row Pointers| R_PTR[""row_ptr: Vec<usize> [0, 3, 7, ...]""]
    CSR_Graph -->|Column Indices| TARG[""targets: Vec<NeuronId>""]
    CSR_Graph -->|Values| WGT[""weights: Vec<f32> (signed)""]
    CSR_Graph -->|Metadata| DEL[""delays: Vec<DelayTicks>""]
    CSR_Graph -->|Metadata| POL[""polarities: Vec<Polarity>""]

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Sources: README.md:38-38, src/lib.rs:50-50, src/topology/graph.rs:18-89

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3. Axonal Delay

Definition

Axonal delay represents the finite propagation time required for an action potential (spike) to travel along an axon from a source neuron to a target synapse, measured in discrete simulation ticks (DelayTicks). A delay of 0 denotes instantaneous (same-tick) delivery src/types.rs:16-18.

Code Entities and Mechanics

Delays are stored alongside weights in descriptors and graph structures src/types.rs:51-64, src/topology/graph.rs:43-44. At runtime, the SynapticMesh orchestrator uses a ring-buffer queue (SpikeDelayBuffer) to inject, advance, and drain delayed spikes across tick boundaries src/lib.rs:48-49, src/lib.rs:96-104.

graph TD
    subcode["Axonal Delay & Ring Buffer Execution"]
    SPK[""Source Spike Vector""] -->|Inject| SDB[""SpikeDelayBuffer (delay ring)""]
    SDB -->|Advance Ticks| DRAIN[""Drain Due Spikes""]
    DRAIN -->|Multiply Weights| CURR[""Synaptic Current Vector (Vec<f32>)""]

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Sources: README.md:34-35, src/lib.rs:48-49, src/types.rs:16-18

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4. Topology Digest

Definition

A topology digest is a versioned, canonical cryptographic fingerprint (SHA-256) of a logical network graph. It incorporates sorted edges, IEEE weight bit patterns, delays, and polarities, ensuring identical logical connectivity structures produce identical digests regardless of internal memory layout order.

Code Entities and Usage

Computed via graph digest functions README.md:41-41, src/lib.rs:31-33, the digest allows precise provenance tracking, manifest validation, and cross-runtime comparison.

Sources: README.md:41-41, src/lib.rs:31-33, src/lib.rs:47-47

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5. Neuromodulators and Neuromodulation

Definition

Neuromodulators represent global or local chemical signaling factors (such as dopamine-gated potentiation or use-it-or-lose-it plasticity decay) that alter neural integration thresholds, passive leaks, and synaptic weights dynamically over time src/router.rs:8-15.

Code Entities

Implemented via the NeuromodNeuron integrative fixed-threshold primitive and the ChannelRouter configuration structure src/router.rs:40-71, src/router.rs:141-178. Note that this component is strictly optional and isolated from the primary SynapticMesh runtime src/router.rs:12-16.

Sources: src/lib.rs:51-64, src/router.rs:3-178

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6. MSRV (Minimum Supported Rust Version)

Definition

The Minimum Supported Rust Version specifies the oldest compiler version on which the crate is guaranteed to compile and pass test suites. For synaptic-wiring, the MSRV is pinned to Rust 1.98.1 README.md:89-90.

Sources: README.md:89-90

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7. Zero-Allocation Path

Definition

A zero-allocation path refers to execution code paths designed to run within tight simulation loops (such as every tick of a spiking neural network) without allocating dynamic heap memory.

Code Entities

The runtime provides explicit caller-owned buffer APIs—SynapticMesh::propagate_into and SynapticMesh::propagate_graded_into—to facilitate heap-free tick execution src/lib.rs:23-26.

Sources: README.md:65-65, src/lib.rs:23-26