firtool-1.141.0

What's Changed

• [RTG] InlineSequences: best-effort mode and traverse nested regions by @maerhart in #9568
• [MooreToCore] Add ToBuiltinInt bitcast conversion by @TaoBi22 in #9591
• [Docs] Continuing migration of documentation to a single Tools page by @cowardsa in #9589
• [circt-reduce] Fix module-name-sanitizer crash with objects by @seldridge in #9584
• [circt-reduce] Fix instance-stubber: ref/property by @seldridge in #9580
• [ImportVerilog] Swap Statements conditions to ToBuiltinInt by @TaoBi22 in #9594
• [RTG][Elaboration] Support symbolic values more generically by @maerhart in #9577
• [circt-reduce] Fix extmodule-instance-remover crash with strings by @seldridge in #9582
• [circt-reduce] Fix firrtl-remove-unused-ports crash with probes by @seldridge in #9583
• [FIRRTL] Add asReset cast op by @fabianschuiki in #9596
• [FIRRTL] Fix canonicalizer infinite loop with const types by @seldridge in #9595
• [circt-reduce] Add FIRRTL LayerDisable reduction by @seldridge in #9599
• [SV] Add elaboration and run-time error/warning/info operations to SV dialect by @uenoku in #9601
• [FIRRTL][CAPI] Update RefType creation to support layers by @unlsycn in #9600
• [Moore] Remove ToBuiltinBoolOp by @TaoBi22 in #9605
• [circt-reduce] Add list-create-element-remover reduction by @seldridge in #9603
• [MooreToCore] Add UnionType conversion support (Fixes #9570) by @m2kar in #9571
• [MooreToCore] Add NoOpConversion by @TaoBi22 in #9607
• [Moore] Add from_builtin_int op by @TaoBi22 in #9606
• [FIRRTL] Make UnknownValueOp CSE-able by @seldridge in #9608
• [MooreToCore] Emit error for unsupported module port types by @m2kar in #9575
• [datapath] Signed Partial Product Generation by @cowardsa in #9592
• [FIRRTL] Add asReset cast support to InferWidths and InferResets by @fabianschuiki in #9610
• Implement support for DisableIff in assertions by @Lauriethefish in #9612
• Update LTL rationale: remove mention of ltl.disable by @Lauriethefish in #9613
• [Python] Add HLMemType and FirMemType bindings to Seq dialect by @yassinz in #9585
• [FIRRTL] Generate annotation code from tablegen by @youngar in #9604
• Bump LLVM to 972cd847efb20661ea7ee8982dd19730aa040c75. by @mikeurbach in #9618
• [ImportVerilog] Make $past result usable by Moore ops by @TaoBi22 in #9621
• [ESI][PyCDE] Support for serial lists by @teqdruid in #9627
• [OM][Evaluator][domaintool] Drop Kind::Unknown by @seldridge in #9617
• [RTG] Add StringType and basic string ops by @maerhart in #9622
• [RTG] Use string values for comments and error messages by @maerhart in #9623
• [ESI] Move runtime test into pycde integration tests by @teqdruid in #9628
• [RTG] More powerful string formatting for labels by @maerhart in #9631
• [Moore] Add builtin for $urandom_range by @Arya-Golkari in #9629
• [datapath] Signed compressor arguments by @cowardsa in #9620
• [Comb] Add a transform to ensure division does not trap/SIGFPE by @jmolloy in #9619
• [ImportVerilog] Allow $past with non-boolean bitvecs by @TaoBi22 in #9626
• [FIRRTL] Add missing #include by @jmolloy in #9636
• [HW] Fix ArrayCreateOp verifier to support typealiases and add optional result type syntax by @Copilot in #9639
• [domaintool] Use type-based domain assignment by @seldridge in #9630
• [Python] Add "result_type" on ArrayCreateOp by @teqdruid in #9640
• [ImportVerilog] Add queue insert/delete ops by @Lauriethefish in #9632
• [ESI][Runtime] Add support for TypeAlias and python for AnyType by @teqdruid in #9641
• [OM] Add reduction patterns for circt-reduce by @seldridge in #9624
• [LTL] Add optional clock operand to PastOp by @TaoBi22 in #9644
• [RTG] Improve source location tracking in some passes by @maerhart in #9645
• [ESI][Runtime] Add C++ type code generation by @teqdruid in #9642
• [PyRTG] Print location information in MLIR output by @maerhart in #9646
• [comb] New Canonicalization ~sext(x) = sext(~x) by @cowardsa in #9637
• Add support for $changed by @Arya-Golkari in #9634
• [ImportVerilog] Fix incorrect changed PastOp construction by @TaoBi22 in #9652
• [Docs] fix typo in Charter.md by @nilscrm in #9650
• [Docs] Remove nonexistent LTL op from LTL rationale by @TaoBi22 in #9653
• [FIRRTL] Refactor LowerTypes to use linear-time port removal, NFC by @uenoku in #9647
• [ESI][Runtime] Fix Windows cibuildwheel builds by @teqdruid in #9616
• [Docs] Fixed small error in SVA representation of $changed in LTL documentation by @Arya-Golkari in #9659
• [FIRRTL][SpecializeOption] Preserve unselected options by @uenoku in #9664
• [FIRRTL] Add pre-allocation for SmallVector, NFC by @uenoku in #9666
• [FIRRTL][LowerXMR] Add inner symbols directly when possible by @seldridge in #9657
• [MooreToCore] Support moore.from_builtin_int as a NoOpConversion by @Arya-Golkari in #9658
• [MooreToCore][Sim] Implementation of queues in Sim by @Lauriethefish in #9651
• [RTG] Add array_append operation by @maerhart in #9662
• [FIRRTL] Add InstanceGraphInstanceOpInterface to InstanceChoiceOp by @uenoku in #9523
• [FIRRTL][LowerLayers] Add inner symbols directly when possible by @seldridge in #9654
• [FIRRTL][LowerSignature] Support InstanceChoice in LowerSignature by @uenoku in #9665
• [circt-verilog] bump Slang to 10.0 by @TaoBi22 in #9667
• [FIRRTL][circt-reduce] Improve port reductions by @seldridge in #9660
• [FIRRTL][OM] Use signed integer attributes by @rwy7 in #9548
• [Sim][MooreToCore] Implement queue insert/delete/(clear) ops by @Lauriethefish in #9668
• [CombFolds] Improve m_Complement matcher to allow pattern nest by @uenoku in #9663
• [HandshakeToHW] Fix crashes when multiple syncs with different numbers of none inputs are used by @zhengyao-lin in #9587
• [MooreToCore] Add support for $info by @Arya-Golkari in #9672
• [MooreToCore] Add pattern for conversion of NegRealOp by @fzi-hielscher in #9678
• [HWAggregateToComb] Support hw.sturct_extruct and hw.struct_create by @uenoku in #9675
• [FIRRTL] Change FInstanceLike to consider multiple referred modules by @uenoku in #9676
• [ImportVerilog] Modify sampled value functions to use Comb operators by @Arya-Golkari in #9656
• [Arc] Add dialect documentation by @fabianschuiki in #9685
• Enable vcpkg binary caching for ESI Runtime Windows wheel builds by @Copilot in #9691
• [FIRRTL][Reduce] Fix module-port-pruner crash with probe ports by @seldridge in #9694
• [ImportVerilog] Pass library files to slang by @rhanqtl in #9680
• [FIRRTL][IMCP] Add conservative support for InstanceChoiceOp by @uenoku in #9692
• [FIRRTL][LayerSink] Support InstanceChoice by @uenoku in #9696
• [FIRRTL] Dedup: fix non-deduplicatable public module handling by @youngar in #9702
• [LTL][ImportVerilog] Add support for $sampled by @Arya-Golkari in #9673
• [LLHD] teach Deseq about projected fields via ValueField keys by @5iri in #9588
• [MooreToCore] Support all NetOp kinds by @rhanqtl in #9635
• [RTG][Elaboration] Materialize values via attributes when possible by @maerhart in #9703
• [PyRTG] Add instruction decorator by @maerhart in #9671
• [RTG] Immediate & Register to_string by @maerhart in #9670
• [PyRTG] Better diagnostics by @maerhart in #9661
• Add LLVM subprojects to .gitignore to speed up LLM context indexing by @uenoku in #9693
• [RTG] Add folders for most set operations by @maerhart in #9190
• [RTG] Support some missing integer operations by @maerhart in #9669
• [RTG] Add register_to_index and index_to_register ops by @maerhart in #9674
• [RTG][LinearScanRegisterAllocationPass] Support dependent registers by @maerhart in #9681
• [ESI] Fix ambiguous ServiceImplRecordOp::create call by @selimsandal in #9707
• [ConvertToLLVM] Add hw::ConstantOp conversion support and tests by @prithayan in #9709
• [RTG] Add map type and attribute by @maerhart in #9706
• [ESI][Runtime] Add Debug DLLs to wheels for Windows by @Copilot in #9687
• [FIRRTL] Add CheckCombLoops handling for InstanceChoiceOp by @uenoku in #9711
• [CalyxToHW] Fix missing i1-to-clock conversion in convertPipelineOp by @selimsandal in #9715
• [SCFToCalyx] Fix incorrect assert in setResultRegs for scf::IfOp by @selimsandal in #9721
• [HW] Add HWVectorization Pass - Part 1: Linear and Reverse by @mafeguimaraes in #9704
• [FIRRTL][SpecializeOption] Erase all options with default flag by @seldridge in #9724
• [RTG][LinearScanRegisterAllocation] Fix nightly by @maerhart in #9728
• [circt-lec] Add lowering from Synth to Comb by @uenoku in #9725
• [ESI][Runtime] Fix paths in Trace and XRT backends by @teqdruid in #9740
• [HW] HWVectorization Part 2: Mixed Permutations by @mafeguimaraes in #9739

New Contributors

• @Arya-Golkari made their first contribution in #9629
• @nilscrm made their first contribution in #9650
• @zhengyao-lin made their first contribution in #9587
• @rhanqtl made their first contribution in #9680
• @selimsandal made their first contribution in #9707

Full Changelog: firtool-1.140.0...firtool-1.141.0