[uart] Signoff Checklist#615
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Just say "Top level design module that meets the comportability requirements is made available."
Also, cross link it to comportability doc.
I will suggest using "design" instead of IP everywhere since we will use these checklist for the top level as well.
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Maybe change this to "All ports for the top level design as indicated in the specification "?
If we say spec is complete, i think the design should have all the ports added in. If there are changes down the road, those modifications can happen later. WDYT?
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I think we'd better remove this item. as IP_TOP covers this.
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Should this be done after V1?
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Please refer the actual checklist spreadsheet. It has the discussion about this.
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Please add section headings here for ease of navigation.
### Documentation
#### DV_PLAN_DRAFT_COMPLETE
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Perhaps make these a bulleted list (here and below)?
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Is this really needed? The act of filling this out and submitting a PR is in itself reflective of this checklist item, which obviates the need for it.
sjgitty
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I put a bunch of comments here, primarily on the checklist template itself.
Not sure if you were intending that to be finalized yet, it still needs a little
bit of work on the wording.
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Might be worth one sentence describing the purpose, something like:
This signoff checklist provides the recommended items to review when
transitioning from one [Hardware Stage](pointer to hw_stages.md) to
another, for both design and verification stages.
Or something like that.
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Probably also want an explanatory:
Under each stage (D1, D2, V1, etc) is a list of criteria, with the name (eg. SPEC_COMPLETE)
and the list of items expected to complete the checklist.
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Need a sentence, something like:
For a transition from D0 --> D1, the following items should be completed.
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I'm misreading this sentence. I think you're intending to say
The unit must not break top level functionality, such as propagating Xs through TLUL interfaces.
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.md files (except for READMEs) should have one sentence per file per MD guidelines.
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I thought both (80 char, a sentence per line) are permitted. Generally, a sentence per line is good for review but the raw text isn't that great to view.
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How about:
It is acceptable to have lint errors and warnings at this stage.
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type name says V1, text says V2
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same sentence as above about D0 --> D1 transition
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need to have a brief sentence here.
This checklist is for Hardware Stage transitions for the UART peripheral.
All checklist items refer to the content in the Checklist File
or something like that.
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Are we changing this to checklist.md instead of sign_off.md?
I might suggest we move it to doc/project instead of doc/rm
but I'll clean that up in another pass.
asb
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Hi Eunchan, many thanks for putting this together. A couple of hopefully easy requests:
- Separate out the addition of
doc/rm/sign_off.mdto a separate commit in the PR - it doesn't make sense under the title of "[uart] Signoff Checklist". I suggest "[doc/rm] Add signoff checklist definitions" or similar. - Sort out the unrelated changes in the commit - to uart.hjson, uart.sv, top_earlgrey.gen.hjson and top_earlgrey.sv
Thanks. I've removed the design change here as #666 was created and contains exact changes there. Also split the commit into two commits, one for |
asb
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Removing my requested changes. This seems good to me in terms of approach and setting up the template markdown file. I defer to @sjgitty and others to mark that the checklist accurately reflects what was discussed in the meeting, which I wasn't present for.
One formatting note: much of these files seem to be wrapped at 80 chars, while we now prefer one line per sentence.
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do you want to change 2 in-progress item to done?
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@moidx I didn't change the SW_FATAL_ERR, could you please update on this item?
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LGTM based on DV test inspection, and interface review against current use cases.
weicaiyang
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LGTM
will create another PR to sign off V3, along with new coverage waiver file
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don't forget to update uart.prj.hjson with that PR
…On Thu, Oct 31, 2019 at 4:30 PM weicaiyang ***@***.***> wrote:
***@***.**** approved this pull request.
LGTM
will create another PR to sign off V3, along with new coverage waiver file
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On Thu, Oct 31, 2019 at 04:39:56PM -0700, Scott Johnson wrote:
don't forget to update uart.prj.hjson with that PR
On Thu, Oct 31, 2019 at 4:30 PM weicaiyang ***@***.***> wrote:
> ***@***.**** approved this pull request.
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> LGTM
> will create another PR to sign off V3, along with new coverage waiver file
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OK. at first, I thought this should be the completed signoff PR (D3,V3). If not,
let me change the commit title also.
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@weicaiyang are the Xcelium warnings fixed?
aytong
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once the remaining V3 item is resolved, update V3 reviewer/signoff rows, and hjson to V3.
msfschaffner
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LGTM. Don't forget to mark D3 Review as Done...
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You mean "TESTPLAN_COMPLETED"?
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Line 182 of this updated file is a bullet point under "PRELIMINARY_ASSERTION_CHECKS_ADDED"
- All DUT outputs have X / unknown checks when out of reset
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OK.. @martin-lueker WDYT? |
While it would be good to have external review, @martin-lueker didn't attend the |
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Hi @eunchan, and all.
However putting aside these concerns about the exact nature of the coverage definitions, and diligence about maintaining V3 status, I think this looks awesome. This is exactly the level of documentation I was hoping when I first read the lifecycle docs. @rasmus-madsen @senelson7 @tunghoang290780, @smcmaster66 I'm interested in hearing your thoughts as well. |
Agree. I think we can check in the coverage report generated by VCS if Synopsis is OK for that. It's a nice report and provides detail statistics of code and function coverage. @sriyerg WDYT?
There is another cov object in uart_agent (hw/dv/sv/uart_agent/uart_agent_cov.sv), which covers baud rate, parity setting etc. These cover-points are protocol related, so we put them in uart_agent. The others (like interrupt, fifo) are in uart/dv/env/uart_env_cov.sv. Will add file links for these coverage in dv plan. |
After helding the signoff meeting (2019-10-28), the UART IP now reached D3/V3 stage at 2019-11-01. Checklist document and project Hjson are updated accordingly. Co-authored-by: Weicai Yang <weicai@google.com>
This is temporary fix until the IP versioning discussion is completed. As PR lowRISC#965 merged, the Azure Pipeline failed on newer PRs. ```log Build log #L1010 Register headers not up-to-date. Regenerate them with 'make -C hw regs'. ``` PR lowRISC#965 didn't include `gpio`, `uart`, `rv_timer` from the collaterals as those IPs were signed off ( lowRISC#676 lowRISC#615 lowRISC#652 ). The azure pipeline checks every IPs' generated register modules. It is good as it can catch this case, which prevents silent upgrade of internal modules in the signed-off IPs. But it is also annoying every PRs from now failed. So, temporary `hw/Makefile` ignores signed-off IPs until better IP versioning rule is suggested. This is related to lowRISC#975 Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
This is Proof-of-Concept for UART Signoff process.
It has checklist for each milestones. It is expected to be
auto-generated by the tool later. It is expected to be revised only to
ResolutionandNote/Collaterals.The doc is prepared by @weicaiyang, @sriyerg, and @eunchan.
Review Doc: https://docs.google.com/document/d/1Dnf61zPXDAgQbyQ-HrSqP3mKQTonv9ulUqLc_8siNq4/edit?ts=5db7195b#