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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Jun 26, 2024 - Python
Cryptocurrency ASIC mining hardware monitor using a simple web interface
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May 1, 2023 - Python
SystemRDL 2.0 language compiler front-end
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May 9, 2024 - Python
A seamless python to Cadence Virtuoso Skill interface
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Apr 24, 2024 - Python
Allo: A Programming Model for Composable Accelerator Design
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Jun 13, 2024 - Python
Control and Status Register map generator for HDL projects
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Mar 5, 2024 - Python
A simplified and standardized interface for Bitcoin ASICs.
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Jun 26, 2024 - Python
Control and status register code generator toolchain
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Nov 8, 2023 - Python
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
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Jun 20, 2024 - Python
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
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May 5, 2024 - Python
Generate UVM register model from compiled SystemRDL input
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Jan 25, 2024 - Python
Import and export IP-XACT XML register models
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Mar 30, 2024 - Python
Antminer monitor and auto-restart tool (Watchdog). 100% Free Software (Libre)
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Dec 20, 2021 - Python
A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix
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May 19, 2024 - Python
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