Moore.io Demo Project
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Updated
Mar 29, 2023 - SystemVerilog
Moore.io Demo Project
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
BDD Gherkin implementation in native SystemVerilog, based on UVM.
A small collection of tutorials and tools for ASIC design.
Logic Analyzer IP Core
UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.
SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip
SystemVerilog Logger
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
Benchmark fo state-of-the-art Precision Scalable MAC Arrays (PSMAs)
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
An open source, parameterized SystemVerilog digital hardware IP library
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