"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
-
Updated
Mar 31, 2023 - SystemVerilog
"Mastering SystemVerilog: From Fundamentals to Advanced Programming Techniques"
Moore.io Demo Project
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
BDD Gherkin implementation in native SystemVerilog, based on UVM.
A small collection of tutorials and tools for ASIC design.
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.
SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip
Benchmark fo state-of-the-art Precision Scalable MAC Arrays (PSMAs)
Logic Analyzer IP Core
ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
SystemVerilog Logger
Add a description, image, and links to the asic topic page so that developers can more easily learn about it.
To associate your repository with the asic topic, visit your repo's landing page and select "manage topics."