AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
Jul 19, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Repository gathering basic modules for CDC purpose
Simple single-port AXI memory interface
An open source, parameterized SystemVerilog digital hardware IP library
SystemVerilog Logger
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip
Benchmark fo state-of-the-art Precision Scalable MAC Arrays (PSMAs)
Logic Analyzer IP Core
FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.
UART controller that uses a master-slave architecture to enstablish a communication with the other device during the configuration process. This repository provides RTL code and testbench for the device synthesis and simulation, as well as a simple driver to use it in your system.
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