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76 public repositories
matching this topic...
Open-source high-performance RISC-V processor
Updated
Aug 15, 2024
Scala
Chisel: A Modern Hardware Design Language
Updated
Aug 15, 2024
Scala
Updated
Aug 13, 2024
Scala
SonicBOOM: The Berkeley Out-of-Order Machine
Updated
Aug 14, 2024
Scala
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Updated
Aug 15, 2024
Scala
Simple RISC-V 3-stage Pipeline in Chisel
Updated
Aug 9, 2024
Scala
The batteries-included testing and formal verification library for Chisel-based RTL designs.
Updated
Aug 6, 2024
Scala
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Updated
Jan 23, 2020
Scala
A Chisel RTL generator for network-on-chip interconnects
Updated
Aug 7, 2024
Scala
A dynamic verification library for Chisel.
Updated
Jun 6, 2024
Scala
high-performance RTL simulator
Updated
Jun 19, 2024
Scala
Provides dot visualizations of chisel/firrtl circuits
Updated
Apr 14, 2023
Scala
(System)Verilog to Chisel translator
Updated
May 20, 2022
Scala
A RISC-V Core (RV32I) written in Chisel HDL
Updated
Jun 12, 2024
Scala
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
Updated
Mar 2, 2023
Scala
Learning how to make RISC-V 32bit CPU with Chisel
Updated
Sep 17, 2021
Scala
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Updated
Apr 11, 2021
Scala
🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Updated
Nov 8, 2023
Scala
A fault-injection framework using Chisel and FIRRTL
Updated
Feb 1, 2023
Scala
Updated
Jul 1, 2020
Scala
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