Simulate incomplete verilog module with python

Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame

parity calculator for the given bit stream

This repository contains the Verilog HDL implementation of a Car Parking System running on an FPGA. The system is designed to manage car entry and exit through two sensors located at the entrance and exit of the car park. It allows registered users to enter the car park by entering their passwords and controls the traffic lights accordingly.

Quick starter project for using Icarus Verilog + Cocotb

Functional Coverage and Constrained Randomization Extensions for Cocotb

Library of hardware accelerators for popular cryptographic hash functions in SystemVerilog

Examples for using pyuvm

Cocotb extension for QSPI verification

This repository contains a simple demo used in a presentation of mine giving a beginner's guide to using CocoTB. The project provides an example of how to use CocoTB for the verification of a simple 8-bit adder.

A cocotb kernel for Jupyter