AI accelerator architectures requiring half the multipliers
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Updated
Mar 28, 2024 - Python
AI accelerator architectures requiring half the multipliers
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Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone compute…
Simulator + benchmark suite for Micro Aerial Vehicle design.
SBTCVM is a virtual machine implementation of a balanced ternary (base 3) computer. Features several compiled languages for ternary software development.
Course files for ECS 154A in Winter Quarter 2020.
Accelerating Recommender model training by leveraging popular choices -- VLDB 2022
CS 211 Computer Architecture at Rutgers University
Computer architecture project : Cache simulator with LRU replacement policy
These are the Python implementations of FIFO, LRU and OPT page replacement algorithms
A simple script to plot the Roofline model for given HW platforms and applications
A Python program for simulating different kinds of computer caches
Virtualização de uma CPU 8-bits, no logisim, com instruções Assembly em formato inspirado no MIPS-Assembly.
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
Developing a MIPS Instruction Interpreter
Curriculum material for teaching computer architecture with MIPS and POWER
Simulates Tomasulo Algorithms with Reorder Buffer
Pymu is a Python-based program that enables legacy software written for the Intel 8086 microprocessor to run on modern systems.
Here I've created a "little" computer architecture with a compiler that can handle any simple task
Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.
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