A graphical processor simulator and assembly editor for the RISC-V ISA
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Updated
May 2, 2024 - C++
A graphical processor simulator and assembly editor for the RISC-V ISA
Custom 16-bit homebrew CPU, emulator, renderer, circuit, and language
Repository to store what we have studied. 📖 We want everyone to get a job through TechnicalNote.
ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
RISC-V CPU simulator for education purposes
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
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ILLIXR: Illinois Extended Reality Testbed
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CERBERUS 2080™, the amazing multi-processor 8-bit microcomputer, featuring Z80, 65C02 and AVR processors.
A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical path, as described by MICRO 2022 paper by Bera et al. (https://arxiv.org/pdf/2209.00188.pdf)
GARDENIA: Graph Analytics Repository for Designing Efficient Next-generation Accelerators
A repository containing the source codes for the Microprocessors and Computer Architecture Laboratory course (UE18CS256) at PES University.
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
Kite: Architecture Simulator for RISC-V Instruction Set
A collection of my cources, lectures, articles and presentations
Very basic implementation of SPM for gem5 simulator (legacy gem5 version)
Memory consistency model checking and test generation library.
A cache reuse and bypass predictor for LLC using the perceptron learning algorithm. Based on Teran et al., MICRO 2016
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