A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog
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Updated
Nov 12, 2023 - SystemVerilog
A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog
This is project is a MIPS Single-Cycle processor with a cache for data memory.
Micro-Programmed Multi-Cycle Processor
GameBoy Audio Processing Unit
🖥️ Digital Design and Computer Architecture
Design of mips pipeline microprocessor architecture using system verilog
5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.
Complete design of a 32-bit 5-stage pipelined MIPS Processor with an L1 cache with snoopy coherency with achieved Gate-level Frequency of 53MHz and fully synthesised on an FPGA
Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
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Designing simple 5-stage pipelined RISC-V processor (Lab assignment of "Computer Architecture" class)
Developing RISC-V CPU
A pipelined (partial) implementation of the RV32I specification
A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.
Vector ASIP for the application of filters to an image 🖼️
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
MIPS Single cycle Verilog Implementation
MIPS multi cycle Verilog Implementation
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