#
fusesoc
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A quick SPI BFM to assist in SPI device testing and development
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Updated
Jan 15, 2024 - SystemVerilog
VeeR EL2 Core
fpga
processor
riscv
rtl
risc-v
open-source-hardware
fusesoc
verilator
riscv32
western-digital
axi4
ahb-lite
asic-design
el2
-
Updated
Oct 31, 2024 - SystemVerilog
VeeR EH1 core
fpga
processor
riscv
rtl
risc
risc-v
open-source-hardware
fusesoc
verilator
riscv32
western-digital
axi4
ahb-lite
asic-design
veer
-
Updated
May 29, 2023 - SystemVerilog
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