A simulation where I can connect virtual logic gates and build virtual CIs.
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Updated
Dec 26, 2022 - C++
A simulation where I can connect virtual logic gates and build virtual CIs.
Assignment 3, Digital Logic Design Lab, Spring 2021, IIT Bombay
CSE-2112 Digital Syatem Design LAb
Playing with ⚡ logic gates to make corresponding ✔ decision making circuits solving 🔌 electronic challenges at hand 🚦
VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design
Different adders code in VHDL and Comparison
This Repository contains the basic VHDL code for different circuits we learn in Computer Architecture. All the provided codes run on EdaPlayground platform, thus divided into testbench code (that goes under testbench.vhd window )and design code (goes under design.vhd) for clarity.
This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
Digital System Design Lab Codes using Verilog
Labwork on Logic Design implementation in Verilog on a Basys3 FPGA Module
✔️ Bit, Bytes and Logical Gates Abstraction
Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.
A repository for some modules I made while learning Verilog
A simple program that converts a binary number into it's two's complement equivalent. This is used within the SimpleBinaryCalculator repository.
A 4bit Multiplier in VHDL
A simple binary calculator based on a system of gates
Download my Redstone World: https://www.planetminecraft.com/project/redstone-circuits-6024948/
Binary adder implementation in the Game of Life written in JavaScript using canvas.
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