Náčrtky a bloková schémata pro (mikro)procesory do předmětu HAW a nejen
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Updated
Aug 30, 2024 - TeX
Náčrtky a bloková schémata pro (mikro)procesory do předmětu HAW a nejen
high instruction-level-parallelism (ILP) using Resource-Flow-Execution
Sumador de dos números de dos dígitos cada uno codificados en ASCII estándar en 7 bits. Restricción: realizar la suma en binario natural.
Design and Development of AES Encryption and Decryption Modules in Verilog HDL for AES128, AES192, and AES256 Algorithms.
Hardware solution for calculating the inverse square root of an IEEE single-precision floating-point number done in Verilog.
Working-zone encoding: Digital Devices Project, Final Examination 2019/2020 - Politecnico di Milano
Some utility programs I created to help simplify my life wrt hw development tool usage
Hardware Description (and Simulation) Library
VGA LCD version of the CRTelecaster from Electronicos Fantasticos
This repository contains an HPC (High Performance Computing) reliability benchmark, carrying out fault injection experiments on a variety of HPC applications, targeting BLAS (Basic Linear Algebra Subroutines) GEMM (GEneral Matrix Multiply) operations.
RISCV processor done in both single cycle and pipeline (with CSR support) form.
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
unipolar dummy load testing utility
Project for Computer Design course.
Instruction Set Architecture and pipeline to implement a new operation in the computer hardware. Submitted the proposal as part of the project description for CSEN 210 taught by Professor Ramzi Nofal at Santa Clara University.
Digital Logic Design project at Politecnico di Milano
Projeto de relógio digital com projeto de arquitetura, assembler e assembly. Feito como Projeto 1 da disciplina Design de Computadores, do 6° semestre de Engenharia da Computação do Insper.
KiCad project and OpenSCAD model for a custom NeoPixel ring which uses a USB-C socket to interface with LEDswarm controller mainboards.
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