Implementation of a Tensor Processing Unit for embedded systems and the IoT.

An FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器，可实现视频压缩。

DisplayPort IP-core

A Python-based IP Core Management Infrastructure.

The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example

USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface

Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.

IP-XACT based CLI-tools

Synthesizable SystemVerilog IP-Core of the I2S Receiver

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC

Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC

Artículos escritos en base al Proyecto Final de la carrera Ingeniería en Computación FCEFyN UNC

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

Python-based IP-XACT parser

Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)

Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation

Microarquitecturas y Softcores - CESE - FIUBA

LaTeX Class for IP Core Documentation

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip