A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Custom 64-bit pipelined RISC processor

Dual-core 16-bit RISC processor

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

Implementation of a custom GPU ISA microarchitecture called GBox16 based around NVIDIA and AMD microarchitectures

8-bit MISC processor with pipelining

Implementation of QuAC v1.0 ISA microarchitecture called CBox16

16-bit RISC processor with von Neumann architecture

My first processor written in HDL language

Accumulator-based 4-bit processor

ISA extension of Ibex core for ASCON lightweight cryptography algorithm

První projekt (CPU s brainfuck-like ISA) z předmětu Návrh počítačových systémů (INP), třetí semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023

Pipelined MIPS CPU architecture implemented in VHDL.

RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100