OpenLane2 example project for integrating an SRAM hard macro and generating GDS.
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Jan 21, 2026
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openlane2
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Pipelined INT8 MAC PE — Full ASIC flow on SKY130 PDK using Yosys, OpenSTA, OpenLane 2
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Mar 13, 2026 - Perl
Complete RTL-to-GDSII implementation of a UART IP Core using Verilog HDL and the OpenLane2 ASIC design flow with the SkyWater SKY130 PDK. Includes RTL design, functional verification, synthesis, physical design, timing analysis, DRC/LVS verification, and final GDSII layout.
uart uart-verilog verilog-hdl yosys uart-protocol asic-verification uart-transmitter uart-receiver vlsi-design openroad asic-design openlane2
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Jul 31, 2026 - Verilog
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