8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

A collection of phase locked loop (PLL) related projects

Arduino Si5351 library tuned for size and click free.

This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.

Support files for blog posts of Zurich Instruments

RFFC2071 C8051F330

sensorless fixed point foc use smo and pll in stm32

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.

Sensorless FOC (PLL estimator) of AC induction motor with field weakening

Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)

All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz

PLL collection for IceStudio

PLL Simulator in SystemC-AMS

Using ADF4351/PLL to get the frequency you want by STM32F103 !

8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

Very minimalistic 20meter transceiver Digital Frequency Synthesizer with 0.96 or 1.3 inch 128x64 OLED Display for Ham-radio use

Library for the Si5351A (10 MSOP - 3 Clocks Only) clock generator IC in the Arduino environment , based on NT7S library.

Bash scipt for loading AD9547/AD9548 configuration (.stp) via I2C