SPI master and SPI slave for FPGA written in VHDL
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Updated
Apr 24, 2021 - VHDL
SPI master and SPI slave for FPGA written in VHDL
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
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IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
This is a digital hardware design of a simple version of SPI communication protocol using VHDL as the HDL.
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