Verilog for ASIC Design
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Updated
Sep 13, 2021 - Verilog
Verilog for ASIC Design
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.
An easy approach for Conway's Game Of Life with Verilog HDL
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
probable journey of RTL coding ft. Chandra Prakash
A real time clock module is designed and simulated in ModelSim. The language used is Verilog HDL.
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
Verilog implementation of a computer architecture project (single-bus processor) on an iCEstick FPGA
A simple MIPS processor in Verilog.
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