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Jun 3, 2024 - Verilog
testbench
Here are 23 public repositories matching this topic...
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May 28, 2024 - Verilog
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
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May 28, 2024 - Verilog
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
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May 21, 2024 - Verilog
This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.
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May 16, 2024 - Verilog
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
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Apr 1, 2024 - Verilog
probable journey of RTL coding ft. Chandra Prakash
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Mar 14, 2024 - Verilog
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
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Oct 20, 2023 - Verilog
Design Verification of Flash, UART, and SDRAM controller for a 32 bit embedded RISC microprocessor using cocotb.
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Oct 15, 2023 - Verilog
An easy approach for Conway's Game Of Life with Verilog HDL
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Sep 21, 2023 - Verilog
Verilog implementation of a computer architecture project (single-bus processor) on an iCEstick FPGA
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Aug 6, 2023 - Verilog
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.
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May 28, 2022 - Verilog
A simple MIPS processor in Verilog.
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Jan 21, 2022 - Verilog
Verilog for ASIC Design
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Sep 13, 2021 - Verilog
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
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May 14, 2021 - Verilog
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