VUnit is a unit testing framework for VHDL/SystemVerilog
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Updated
Jul 21, 2024 - VHDL
VUnit is a unit testing framework for VHDL/SystemVerilog
Image Processing Toolbox in Verilog using Basys3 FPGA
Proyecto desarrollado para la asignatura de Laboratorio de Electrónica Digital
To receive the clock and data from clock and data interfaces, apply the DSP algorithm on the transmitted data. The DSP algorithm includes differential encoding, scrambling and convolutional encoding, generate test data pattern to be used in the self-test mode of operation
Crane Game using Custom Pipelined Processor
The purpose is to investigate latches, flip-flops, and registers. DA CS 603
Implementation of a Canny-Edge Detector on a Zybo-Z7 FPGA.
Implementation of a sampler using the XADC mounted on the Arty A7-35T development board and the PmodAD1 by Digilent (AD7476A).
The implementation of a Five-Stage Pipelining RISC-V Microprocessor in Verilog HDL
This repository is intended for students who study Electrical Engineering at University of Baghdad, as well as anyone else who wants to learn about FPGA programming.
Verilog sources for FPGA Zybo board implementing vision algorithms.
Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.
Some examples of Veitch-Karnaugh maps solved using verilog language developed as coursework of Architecture and Computer Organization I- @puc Minas
this repo contains 2 assignments during my computer organization and architecture course.
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