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vitis

Here are 21 public repositories matching this topic...

Xilinx / XRT

Run Time for AIE and FPGA based platforms

fpga linux-kernel xrt vitis

Updated Nov 8, 2024
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fpgasystems / Vitis_with_100Gbps_TCP-IP

100 Gbps TCP/IP stack for Vitis shells

tcp xilinx vitis network-kernel

Updated Apr 23, 2024
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definelicht / hlslib

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

cmake fpga hpc xilinx sdaccel high-level-synthesis vivado-hls intel-fpga vitis intel-fpga-opencl

Updated Apr 23, 2024
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Xilinx / Vitis_Model_Composer

Vitis Model Composer Examples and Tutorials

fpga hls acap vitis aiengine

Updated Nov 8, 2024
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Xilinx / xup_compute_acceleration

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

fpga xilinx vitis xup

Updated Jul 24, 2024
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spcl / apfp

FPGA acceleration of arbitrary precision floating point computations.

fpga hls hpc bignum arbitrary-precision high-performance-computing xilinx gmp mpfr high-level-synthesis vivado-hls vitis multiple-precision

Updated May 17, 2022
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ros-acceleration / vitis_common

Common code for working with Vitis™ Unified Software Platform in ROS 2.

fpga robotics hardware xilinx hardware-acceleration ros2 vitis

Updated Nov 18, 2022
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jasonlin316 / GCN-Inference-Acceleration-HLS

An end-to-end GCN inference accelerator written in HLS

neural-network hls end-to-end inference xilinx gcn vitis

Updated Apr 5, 2022
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salehjg / DeepPoint-V2-FPGA

The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs

fpga deep-learning hls xilinx pointcloud sdaccel shapenet-dataset modelnet-dataset vitis

Updated Mar 6, 2023
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kaanolgu / matrix_multiplications

Vitis 2020.1 Acceleration Examples and Developed Large Size Matrix Multiplication Examples

vitis alveo-u200 matrix-multiplications vitis-acceleration

Updated Nov 1, 2020
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autohdw / flames

Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)

fpga hls cpp linear-algebra high-level-synthesis vitis vitis-hls

Updated Nov 5, 2024
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cothan / Vitis_High_Level_Synthesis_Training

Vitis High Level Synthesis Introduction

fpga high-performance neon armv7 hardware-acceleration high-level-synthesis armv8-a vitis vitis-acceleration

Updated Apr 20, 2021
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Low_Order_FIRs_in_AIE

cholmber / Low_Order_FIRs_in_AIE

Practical coding guidelines for AI Engine kernel development, plus clear explanations of squares and indexing

filter fir intrinsic aie permute vitis vitis-acceleration xsquare zsquare

Updated Feb 26, 2021
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FrankKesel / xilinx_tools

Xilinx Tools Tutorials

fpga vhdl xilinx xilinx-fpga xilinx-vivado high-level-synthesis vitis xilinx-vitis vitis-hls

Updated Nov 6, 2024
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BabarZKhan / tapasco_counter_versions

acceleration fpga xilinx-fpga vitis

Updated Apr 19, 2021
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ChienKaiMa / 2021_ACA_HLS_team05

High level synthesis projects and practices

fpga hls xilinx vivado xilinx-fpga xilinx-vivado high-level-synthesis vivado-hls pynq-z2 vitis

Updated Apr 13, 2021
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beetleboxorg / Getting-started-with-BeetleboxCI-and-Vitis-Running-FAST

Learn how to get started with BeetleboxCI and Vitis Unified Development Environment with this tutorial covering using computer vision on FPGA technology

computer-vision fpga vitis beetleboxci

Updated Apr 5, 2023
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vishalcseiitg / CS-577-C-BASED-VLSI-DESIGN

Course taken by Dr Chandan Karfa of Dept. of CSE, IIT Guwahati.

fpga cpp hardware verilog-hdl vivado-hls vitis

Updated Mar 23, 2023
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KasraAhmadi / window_method_error_detection

Error detection enabled Window method scalar multiplication on Elliptic Curves

python simulation ecc elliptic-curves error-detection vitis ecsm

Updated Jan 19, 2024
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jlscheerer / matrix-profile-hls

Systolic array-based Matrix Profile Computation implemented in Vitis™ HLS for Xilinx FPGAs.

cmake fpga hls hpc opencl high-level-synthesis matrix-profile vitis

Updated Sep 7, 2021
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