Logic Analyzer IP Core
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Updated
Jul 23, 2022 - SystemVerilog
Logic Analyzer IP Core
Library containing various VHDL IPs
Developing RISC-V CPU
For finalizing experimental development work on the mksocfpga_hm3 repo back into machinekit
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
Notes after working with Zynq platform using vivado and petalinux
A 480p (VGA) 16 bit sprite rendering processing unit
8-bit multiplier module implemented on SystemVerilog meant for the xc7s50csga324-1 Spartan 7 FPGA
This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language
running ANN on an FPGA
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
learning about FPGA
An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)
NESystem Verilog
This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.
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