vivado
Here are 28 public repositories matching this topic...
Developing RISC-V CPU
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Jan 29, 2024 - SystemVerilog
For finalizing experimental development work on the mksocfpga_hm3 repo back into machinekit
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Jan 2, 2018 - SystemVerilog
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
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Apr 23, 2024 - SystemVerilog
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
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Feb 16, 2024 - SystemVerilog
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
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Aug 24, 2023 - SystemVerilog
This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language
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Apr 11, 2024 - SystemVerilog
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
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Apr 23, 2024 - SystemVerilog
learning about FPGA
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May 20, 2024 - SystemVerilog
A 480p (VGA) 16 bit sprite rendering processing unit
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Feb 3, 2021 - SystemVerilog
8-bit multiplier module implemented on SystemVerilog meant for the xc7s50csga324-1 Spartan 7 FPGA
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Sep 23, 2023 - SystemVerilog
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
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May 4, 2024 - SystemVerilog
NESystem Verilog
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Jan 8, 2023 - SystemVerilog
VHDL implementation of VGA controller. Implemented on Zybo Zynq-7000 board which uses switches to change output color.
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May 12, 2019 - SystemVerilog
Notes after working with Zynq platform using vivado and petalinux
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Feb 26, 2024 - SystemVerilog
An cellular automata game for a 8x8 matrix on the BetiBoard. (requires Basys3 board)
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Mar 20, 2020 - SystemVerilog
This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.
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Jul 9, 2022 - SystemVerilog
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