HITSZ 2024 数字电路技术实验 FPGA Verilog 代码仓库
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Updated
Jun 12, 2024 - Verilog
HITSZ 2024 数字电路技术实验 FPGA Verilog 代码仓库
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A verilog program that keeps count of the number of cars enter a parking lot and how many spots are free. Code made in Verilog for AMD FPGA xc7s50csga324-1 boolean board
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
Sobel Filter Verilog implementation
This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
FPGA based analog signal generator with DAC
Digital Piano: FPGA project in Verilog based on Xilinx Atrix-7 EGO1 - SUSTech's project of course CS207: Digital Logic in Fall 2023 - Score: 120/100
Dual-Mode PSK Transceiver on SDR With FPGA
This project aims to design a hardware encryption and decryption scheme for the Data Encryption Standard (DES) algorithm
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