A VHDL implementation of a MIPS processor with multicycle instruction fetching
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Updated
Mar 27, 2020 - C
A VHDL implementation of a MIPS processor with multicycle instruction fetching
Displays colorwheel on OLED display in HSV scale on Xilinx Nexys 4DDR FPGA
This repository contains the implementation of Image Processing Benchmarks running on Arm Cortex-A9 processor available in Xilinx Zynq 7000 SoC on Avent Zedboard.
Zynq-7000 PS side drivers for SLCR Registers.
Design for FPGA of a Universal Asynchronous Receiver Transmitter.
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
PID control on Xilinx Nexys 4DDR FPGA board using XilKernel
Using Xlinix SDK and a Basys 3 board, joystick, motor, and LCD screen to simulate a DC motor winch with information being displayed on the LCD screen
In the repository I have implemented a ALU with Finite State machine with VHDL and Xilinx ISE 14.7 application. Also a BCD to seven segment have been implemented for input and output digits.
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
Xilinix VHDL Projects
Small C program to convert a bin file to COE; a format used by Xilinx to load memory contents.
Adaptive Computer Challenge Project @ Hackster.IO
ILI9488 TFT SPI display library for Xilinx SoC and FPGA
My own project in VHDL using ISE Xilinx and FPGA component xc3s200-5ft256
This version of crispy-DOOM uses 8 HW accelerators on the FPGA
Audio Sampler for Zybo
Video game made for E2LP, FPGA board, as a project for course Logic Design of Computer Systems 2
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