xilinx
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Simple audio processing with ADAU1761
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Apr 18, 2020 - Tcl
TCL scripts for FPGA (Xilinx)
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Jul 5, 2022 - Tcl
Case study of synchronous FPGA signaling by adjusting the output timing
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Aug 16, 2019 - Tcl
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
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May 1, 2020 - Tcl
Keep Xilinx Vivado projects as minimal git repositories. A fork of https://github.com/Digilent/digilent-vivado-scripts
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Aug 13, 2024 - Tcl
Base project used to create new Vivado designs compatible with git
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Nov 21, 2020 - Tcl
Introduction to VHDL and Digital Logic - Basys 3 and Vivado Projects Repository
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Mar 5, 2024 - Tcl
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
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Aug 8, 2020 - Tcl
HLS-based Xilinx ICAP3 Controller (tested with VCU108)
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Jan 18, 2020 - Tcl
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