DSLogic

DreamSourceLab DSLogic

Besides its own boards, openSciLab drives the USB logic analyzers DSLogic Plus, DSLogic U2Pro16, DSLogic U3Pro16 and DSLogic U3Pro32 of DreamSourceLab. This page covers what is needed to use them, the capture settings they offer and the self-test.

Experimental. The driver follows the open source DSLogic driver of DSView (GPL). It has been tested on a U2Pro16; the other models have not been tried on hardware yet. Reports – with the log of openscilab --debug-driver – are welcome.

What you need

• The DSView firmware on the board. The analyzers start the firmware of current DSView versions from their own memory. A U3 model without it is refused with a message: connect it once to DSView, which updates its firmware, then try again. A Plus or U2Pro16 that waits for its firmware gets it loaded from DSView's res folder (an installed DSView or the folder you chose, see below).

• The FPGA bitstream. The FPGA design of the DSLogic is not open source, so its bitstreams (DSLogicPlus.bin, DSLogicU2Pro16.bin, DSLogicU3Pro16.bin, DSLogicU3Pro32.bin, ...) are not part of openSciLab. They are taken from an installed DSView (its res folder is found in the usual places). Without DSView, openSciLab asks FPGA bitstream needed when the analyzer is connected:

  • Download from DSView fetches the file once from the DSView repository on GitHub – a fixed version, checked by its SHA-256 – into the settings directory;
  • Choose DSView folder... takes it from the res folder of a DSView elsewhere, e.g. C:\Program Files\DSView\res.

  On the command line, --download-bitstream does the download.

• Access to the USB device. The USB library (libusb) comes with openSciLab.

  • Linux: install the udev rule packaging/linux/60-dslogic.rules, then unplug the analyzer and plug it in again:

    sudo cp 60-dslogic.rules /etc/udev/rules.d/
    sudo udevadm control --reload-rules && sudo udevadm trigger

  • Windows: the WinUSB driver that DSView installs is used. Without DSView, install WinUSB for the analyzer with Zadig.

• No DSView running at the same time. DSView and openSciLab cannot use the analyzer together; openSciLab says so when the analyzer is busy.

Connecting

A connected DSLogic appears in the device list under Available with its model, USB speed and bus position, e.g. DSLogic U2Pro16 (USB 2, 1:4). Double-click it (or use Devices → Connect...). Opening it loads the FPGA, which takes a few seconds; it runs in the background. The analyzer is read in a process of its own, like the Pico and Arduino boards (Settings → Devices).

Its device card has the tabs Pins, Timing and Details (see Devices); Capture... opens its data view.

Capture settings

The capture settings of the data view (see Data view) offer the rates of the analyzer as a list that depends on the selected channels, as in DSView:

Model	Buffer (device memory)	Stream (over USB)
DSLogic Plus (256 Mbit)	100 MHz with channels 1–16, 200 MHz with 1–8, 400 MHz with 1–4	20 MHz with 16, 25 MHz with 12, 50 MHz with 6, 100 MHz with 3 channels
DSLogic U2Pro16 (4 Gbit)	500 MHz with channels 1–16, 1 GHz with 1–8	20 MHz with 16, 25 MHz with 12, 50 MHz with 6, 100 MHz with 3 channels
DSLogic U3Pro16 (2 Gbit)	500 MHz with channels 1–16, 1 GHz with 1–8	USB 3: 125 MHz with 16, 250 MHz with 12, 500 MHz with 6 channels, 1 GHz with 3 of channels 1–8; USB 2: as the U2Pro16
DSLogic U3Pro32 (2 Gbit)	250 MHz with channels 1–32, 500 MHz with 1–16, 1 GHz with 1–8	USB 3: 50 MHz with 32, 100 MHz with 30, 250 MHz with 12, 500 MHz with 6 of channels 1–16, 1 GHz with 3 of channels 1–8; USB 2: 10 MHz with 32 up to 100 MHz with 3 channels

• Acquisition: Buffer (device memory) keeps the capture in the memory of the analyzer, which the enabled channels share – the fastest rates. Stream (over USB) sends the samples while capturing and allows much longer captures at lower rates.
• A stream is shown while it runs, following its end; zoom or scroll back at any time. Stop keeps the samples received so far, and the decoders run when it ends.
• Until stopped: the stream runs until Stop (up to 2³⁶ samples, about an hour at 20 MHz) and keeps only its latest samples, as many as the sample count says.
• Record to disk: the stream goes into memory-mapped files instead of memory. The operating system keeps only the parts in use in RAM; the limit is the free disk space less 4 GB (an endless stream uses half of it) instead of about one billion samples. The files hold one byte per sample and channel: at 20 MHz with 16 channels that is 320 MB/s, about 19 GB per minute. Decoders then run on request (Decode now on the Decoders tab of the data view). A disk that fills up stops the stream and keeps what arrived. The files are deleted with the capture.
• Threshold: the input voltage above which a sample reads as 1, 0 to 5 V, 1.0 V by default.
• A capture held in memory has at most about one billion samples over all channels.

Triggers

• Edge: a rising or falling edge on any channel.
• Pattern: a level pattern on consecutive channels.
• None: the capture starts at once.

On a stream, Evaluate the trigger in the application (on a stream, at the stream rates) looks for any trigger – also a trigger sequence of patterns, edges, pulse widths and gaps – in the samples as they arrive; see Data view. Blast mode and bursts belong to the Pico boards and are not offered for the DSLogic.

Self-test

Self-test... on the Details tab of the device card, then Run self-test. The FPGA captures its internal test counter instead of the inputs, which checks the capture memory, the USB transfer in buffer and stream mode and the pattern and edge triggers bit by bit, without any signal. The test also lists the firmware, the FPGA, the USB speed and the security check of the board, and reports every input that does not read low – disconnect the probes before running it.

Command line

The address of a DSLogic is dslogic (the first one) or dslogic:<bus>:<address>:

openscilab-cli devices
openscilab-cli info dslogic --download-bitstream

See Scripting for captures from the command line and from Python.