Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Submission template for TT02

Cryptocurrency ASIC mining hardware monitor using a simple web interface

SystemRDL 2.0 language compiler front-end

A simplified and standardized interface for Bitcoin ASICs.

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

A seamless python to Cadence Virtuoso Skill interface

The next generation of OpenLane, rewritten from scratch with a modular architecture

Control and Status Register map generator for HDL projects

Allo: A Programming Model for Composable Accelerator Design

Generate UVM register model from compiled SystemRDL input

Primitives for GF180MCU provided by GlobalFoundries.

Control and status register code generator toolchain

Bruteforce tool for AsicMiner and Awesome Miner

tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles

HW Design: A Functional Approach

Import and export IP-XACT XML register models

Unofficial python api for MicroBT Whatsminer ASICs

Antminer monitor and auto-restart tool (Watchdog). 100% Free Software (Libre)